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參數(shù)資料
| 型號： | TB310 |
| 廠商： | Intersil Corporation |
| 英文描述： | Decimating Digital Filter |
| 中文描述： | 元氣，數(shù)字濾波 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | TB310 |
3-194
HSP43220
Decimating Digital Filter
The HSP43220 Decimating Digital Filter is a linear phase
low pass decimation filter which is optimized for filtering
narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220 offers a single chip
solution to signal processing applications which have
historically required several boards of ICs. This reduction in
component count results in faster development times as well
as reduction of hardware costs.
The HSP43220 is implemented as a two stage filter
structure. As seen in the block diagram, the first stage is a
high order decimation filter (HDF) which utilizes an efficient
sample rate reduction technique to obtain decimation up to
1024 through a coarse low-pass filtering process. The HDF
provides up to 96dB aliasing rejection in the signal pass
band. The second stage consists of a finite impulse
response (FIR) decimation filter structured as a transversal
FIR filter with up to 512 symmetric taps which can implement
filters with sharp transition regions. The FIR can perform
further decimation by up to 16 if required while preserving
the 96dB aliasing attenuation obtained by the HDF. The
combined total decimation capability is 16,384.
The HSP43220 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 33 MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220 also provides the capability to bypass either the
HDF or the FIR for additional flexibility.
Features
Single Chip Narrow Band Filter with up to 96dB
Attenuation
DC to 33MHz Clock Rate
16-Bit 2’s Complement Input
20-Bit Coefficients in FIR
24-Bit Extended Precision Output
Programmable Decimation up to a Maximum of 16,384
Standard 16-Bit Microprocessor Interface
Filter Design Software Available DECIMATE
Up to 512 Taps
Applications
Very Narrow Band Filters
Zoom Spectral Analysis
Channelized Receivers
Large Sample Rate Converter
Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HSP43220VC-33
0 to 70
100 Ld MQFP
Q100.14x20
HSP43220JC-15
0 to 70
84 Ld PLCC
N84.1.15
HSP43220JC-25
0 to 0
84 Ld PLCC
N84.1.15
HSP43220JC-33
0 to 70
84 Ld PLCC
N84.1.15
HSP43220GC-25
0 to 70
84 Ld CPGA
G84.A
HSP43220GC-33
0 to 70
84 Ld CPGA
G84.A
DECIMATE
Software Development Tool (This software tool may be
downloaded from our Internet site: http://www.intersil.com)
INPUT CLOCK
DATA INPUT
DATA OUT
FIR CLOCK
DECIMATION UP TO 1024
DECIMATION UP TO 16
DATA READY
24
CONTROL AND COEFFICIENTS
16
16
FIR
DECIMATION
FILTER
HIGH ORDER
DECIMATION
FILTER
Data Sheet
February 1999
File Number
2486.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
DECIMATE is a trademark of Intersil Corporation.
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