參數(shù)資料
型號: TAS5704PAPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: GREEN, PLASTIC, HTQFP-64
文件頁數(shù): 35/38頁
文件大小: 735K
代理商: TAS5704PAPR
SLOS563A – MARCH 2008 – REVISED AUGUST 2010
www.ti.com
PIN FUNCTIONS (continued)
PIN
5-V
TERMINATION
TYPE
DESCRIPTION
TOLERANT
(2)
NAME
NO.
(1)
BST_B
61
P
High-side bootstrap supply for half-bridge B
BST_C
53
P
High-side bootstrap supply for half-bridge C
BST_D
55
P
High-side bootstrap supply for half-bridge D
BYPASS
56
O
Nominally equal to VCC/8. Internal reference voltage for analog cells
CONFIG_1
34
P
Pulldown
Input/output configuration.
CONFIG_2
33
P
Pulldown
Input/output configuration.
DVDD
15,
P
3.3-V digital power supply
35
DVSS
26
P
Digital ground
DVSSO
20
P
Oscillator ground
FORMAT0
32
DI
Pulldown
Digital data format select.
FORMAT1
31
DI
Pulldown
Digital data format select.
FORMAT2
30
DI
Digital data format select.
GAIN_0
29
DI
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
GAIN_1
28
DI
MSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
LRCLK
22
DI
5-V
Input serial audio data left/right clock (sampling rate clock)
MCLK
36
DI
5-V
Master clock input. The input frequency of this clock can range from
4.9 MHz to 49.2 MHz.
MUTE
21
DI
5-V
Pullup
Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
OSC_RES
19
AO
Oscillator trim resistor. Connect an 18.2-k
resistor to DVSSO.
OUT_A
4, 5
O
Output, half-bridge A
OUT_B
1, 64
O
Output, half-bridge B
OUT_C
49,
O
Output, half-bridge C
50
OUT_D
45,
O
Output, half-bridge D
46
PDN
17
DI
5-V
Pullup
Power down, active-low. PDN stops all clocks and outputs stop
switching. When PDN is released, the device powers up all logic,
starts all clocks, and performs a soft start that returns to the previous
configuration. Changes to CONFIG_x, FORMATx, and GAIN_x pins
are ignored on PDN cycling.
PGND_A
6, 7
P
Power ground for half-bridge A
PGND_B
2, 3
P
Power ground for half-bridge B
PGND_C
47,
P
Power ground for half-bridge C
48
PGND_D
43,
P
Power ground for half-bridge D
44
PLL_FLTM
12
AO
PLL negative loop filter terminal
PLL_FLTP
13
AO
PLL positive loop filter terminal
PVCC_A
8, 9
P
Power supply input for half-bridge output A
PVCC_B
62,
P
Power supply input for half-bridge output B
63
PVCC_C
51,
P
Power supply input for half-bridge output C
52
PVCC_D
41,
P
Power supply input for half-bridge output D
42
6
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5704
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TAS5704PAP 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
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