參數(shù)資料
型號(hào): TAS5704PAPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù): 14/38頁(yè)
文件大?。?/td> 735K
代理商: TAS5704PAPR
1/fS
(= 32 fS, 48 fS, or 64 fS)
L-Channel
R-Channel
LRCK
SLCK
DATA
N1
N2
N3
0
N1
N2
N3
0
1
2
MSB
LSB
MSB
1
2
N–1
N–2
LRCK
MSB
LSB
1/fS
(= 32 fS, 48 fS, or 64 fS)
18-Bit Right-Justified, SCLK = 48 fS or 64 fS
MSB
LSB
20-Bit Right-Justified, SCLK = 48 fS or 64 fS
LSB
16-Bit Right-Justified, SCLK = 48 fS or 64 fS
16-Bit Right-Justified, SCLK = 32 fS
LSB
L-Channel
R-Channel
SCLK
DATA
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
DATA
17 16 15
2
1
0
2
1
0
19 18 17
2
1
0
MSB
LSB
MSB
LSB
MSB
LSB
15 14 13
2
1
0
2
1
0
17 16 15
2
1
0
19 18 17
2
1
0
MSB
15 14 13
MSB
15 14 13
MSB
15 14 13
24-Bit Right-Justified, SCLK = 48 fS
LSB
DATA
2
1
0
2
1
0
MSB
LSB
23 22 21
2
1
0
MSB
23 22 21
LSB
24-Bit Right-Justified, SCLK = 64 fS
2
1
0
2
1
0
DATA
LSB
2
1
0
MSB
23 22 21
MSB
23 22 21
www.ti.com
SLOS563A – MARCH 2008 – REVISED AUGUST 2010
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fs is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
Figure 27. Left-Justified Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fs is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks
unused leading data bit positions.
Figure 28. Right-Justified Format
Copyright 2008–2010, Texas Instruments Incorporated
21
Product Folder Link(s): TAS5704
相關(guān)PDF資料
PDF描述
TAS5704PAP 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
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TAS5705PAPRG4 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
TAS5705PAPR 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
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