
SLAS711B
– JUNE 2010 – REVISED SEPTEMBER 2011
PIN FUNCTIONS (continued)
PIN
FUNCTION(1)
DESCRIPTION
NAME
PHD NO.
DKD NO.
INPUT_A
4
6
I
Input signal for half bridge A
INPUT_B
5
7
I
Input signal for half bridge B
INPUT_C
10
12
I
Input signal for half bridge C
INPUT_D
11
13
I
Input signal for half bridge D
M1
20
I
Mode selection
M2
21
I
Mode selection
M3
22
I
Mode selection
NC
59-62
–
No connect, pins may be grounded.
OC_ADJ
1
3
O
Analog over current programming pin requires 30k
resistor to ground:
OSC_IO+
13
15
I/O
Oscillator master/slave output/input.
OSC_IO
–
14
16
I/O
Oscillator master/slave output/input.
/OTW
-
18
O
Overtemperature warning signal, open drain, active low.
OTW1
16
–
O
Overtemperature warning signal, open drain, active low.
OTW2
17
–
O
Overtemperature warning signal, open drain, active low.
OUT_A
52, 53
39, 40
O
Output, half bridge A
OUT_B
44, 45
36
O
Output, half bridge B
OUT_C
36, 37
31
O
Output, half bridge C
OUT_D
28, 29
27, 28
O
Output, half bridge D
PSU_REF
63
1
P
PSU Reference requires close decoupling of 330pF to GND
Power supply input for half bridges A requires close decoupling of 2
μF capacitor to
PVDD_A
50, 51
41, 42
P
GND_A.
Power supply input for half bridges B requires close decoupling of 2
μF capacitor to
PVDD_B
42, 43
35
P
GND_B.
Power supply input for half bridges C requires close decoupling of 2
μF capacitor to
PVDD_C
38, 39
32
P
GND_C.
Power supply input for half bridges D requires close decoupling of 2
μF capacitor to
PVDD_D
30, 31
25, 26
P
GND_D.
READY
19
O
Normal operation; open drain; active high
RESET
2
4
I
Device reset Input; active low, requires 47k
pull up resistor to VREG
SD
15
17
O
Shutdown signal, open drain, active low
Power supply for internal voltage regulator requires a 10-
μF capacitor with a 0.1-μF
VDD
64
2
P
capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 1nF to GND
VREG
9
11
P
Internal regulator supply filter pin requires 0.1-
μF capacitor to GND
6
Copyright
2010–2011, Texas Instruments Incorporated