PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, T" />
參數(shù)資料
型號(hào)： TAS5613ADKDR
廠商： Texas Instruments
文件頁(yè)數(shù)： 2/33頁(yè)
文件大?。?/td> 0K
描述： IC AMP AUD 150W STER D 44HSSOP
標(biāo)準(zhǔn)包裝： 1
系列： PurePath™ HD
類型： D 類
輸出類型： 1-通道（單聲道）或 2-通道（立體聲）
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 300W x 1 @ 2 歐姆; 200W x 2 @ 3 歐姆
電源電壓： 18 V ~ 38 V
特點(diǎn)： 消除爆音，差分輸入，短路和熱保護(hù)，關(guān)閉
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 44-HSSOP
封裝/外殼： 44-BSSOP（0.433"，11.00mm 寬）裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 296-29706-6
SLAS711B
– JUNE 2010 – REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 400kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference node
VDD = 12V
3
3.3
3.6
V
Analog comparator reference node, VI_CM
1.5
1.75
1.9
V
Operating, 50% duty cycle
20
IVDD
VDD supply current
mA
Idle, reset mode
20
50% duty cycle
10
IGVDD_x
Gate-supply current per half-bridge
mA
Reset mode
1.5
50% duty cycle with recommended output filter
12.5
mA
IPVDD_x
Half-bridge idle current
Reset mode, No switching
620
μA
ANALOG INPUTS
RIN
Input resistance
READY = HIGH
33
k
VIN
Maximum input voltage swing
7
V
IIN
Maximum input current
1
mA
G
Inverting voltage Gain, (VOUT/VIN)
21
dB
OSCILLATOR
Nominal, Master Mode
3.85
4
4.15
fOSC_IO+
AM1, Master Mode
FPWM × 10
3.15
3.33
3.5
MHz
AM2, Master Mode
2.6
3
3.35
VIH
High level input voltage
1.86
V
VIL
Low level input voltage
1.45
V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
60
100
m
TJ = 25°C, Includes metallization resistance,
RDS(on)
GVDD = 12V
Drain-to-source resistance, high side (HS)
60
100
m
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
Vuvp,G
9.5
V
VDD
Vuvp,hyst
(1)
0.6
V
Overtemperature warning 1, OTW1(1)
95
100
105
°C
OTW
Overtemperature warning 2, OTW, OTW2(1)
115
125
135
°C
Temperature drop needed below OTW
OTWHYST
(1)
temperature for OTW to be inactive after OTW
25
°C
event.
OTE(1)
Overtemperature error
145
155
165
°C
OTE-OTWdifferential
OTE-OTW differential
30
°C
(1)
A reset needs to occur for SD to be released
OTEHYST
(1)
25
°C
following an OTE event
OLPC
Overload protection counter
fPWM = 400kHz
2.6
ms
Resistor
– programmable, nominal peak current in
14
1
load, ROCP = 30k
IOC
Overcurrent limit protection
A
Resistor
– programmable, nominal peak current in
1
load, ROCP = 22k (with Schottky diodes on
18
output nodes)
Resistor
– programmable, peak current in 1 load,
14
ROCP = 64k
IOC_LATCHED
Overcurrent limit protection
A
Resistor
– programmable, nominal peak current in
1
load, ROCP = 47k (with Schottky diodes on
18
output nodes)
Time from switching transition to flip-state induced
IOCT
Overcurrent response time
150
ns
by overcurrent.
Connected when RESET is active to provide
IPD
Output pulldown current of each half
3
mA
bootstrap charge. Not used in SE mode.
(1)
Specified by design.
10
Copyright
2010–2011, Texas Instruments Incorporated
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