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Powering Down
Use
Capable Systems
of
TAS5142
in
High-Modulation-Index
ERROR REPORTING
The
SD
and
open-drain outputs. Their function is for protec-
tion-mode signaling to a PWM controller or other
system-control device.
Overcurrent
Limiting and Overload Detection
(OC)
Protection
With
Current
DEVICE PROTECTION SYSTEM
The TAS5142 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from
permanent failure due to a wide range of fault
conditions
such
as
short
TAS5142
SLES126B–DECEMBER 2004–REVISED MAY 2005
overtemperature, and undervoltage. The TAS5142
responds to a fault by immediately setting the power
stage in a high-impedance (Hi-Z) state and asserting
the SD pin low. In situations other than overload, the
device automatically recovers when the fault con-
dition has been removed, i.e., the junction tempera-
ture has dropped or the supply voltage has in-
creased. For highest possible reliability, recovering
from an overload fault requires external reset of the
device (see the
Device Reset
section of this data
sheet) no sooner than 1 second after the shutdown.
The TAS5142 does not require a power-down se-
quence. The device remains fully operational as long
as the gate-drive supply (GVDD_X) voltage and VDD
voltage are above the undervoltage protection (UVP)
voltage threshold (see the
Electrical Characteristics
section of this data sheet). Although not specifically
required, it is a good practice to hold RESET_AB and
RESET_CD low during power down, thus preventing
audible artifacts including pops or clicks.
When the TAS5142 is being used with TI PWM
modulators such as the TAS5508, no special atten-
tion to the state of RESET_AB and RESET_CD is
required, provided that the chipset is configured as
recommended.
This device requires at least 50 ns of low time on the
output per 384-kHz PWM frame rate in order to keep
the bootstrap capacitors charged. As an example, if
the modulation index is set to 99.2% in the TAS5508,
this setting allows PWM pulse durations down to 20
ns. This signal, which does not meet the 50-ns
requirement, is sent to the PWM_X pin and this
low-state pulse time does not allow the bootstrap
capacitor to stay charged. In this situation, the low
voltage across the bootstrap capacitor can cause a
failure of the high-side MOSFET transistor, especially
when driving a low-impedance load. The TAS5142
device requires limiting the TAS5508 modulation
index to 96.1% to keep the bootstrap capacitor
charged under all signals and loads.
OTW
pins
are
both
active-low,
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125
°
C (see
the following table).
SD
0
OTW
0
DESCRIPTION
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
Overload (OLP) or undervoltage (UVP)
Junction temperature higher than 125°C
(overtemperature warning)
Junction temperature lower than 125°C and no
OLP or UVP faults (normal operation)
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5508 or TAS5086, with the
modulation index set at 96.1% to interface with
TAS5142.
0
1
1
0
1
1
Note that asserting either RESET_AB or RESET_CD
low forces the SD signal high, independent of faults
being present. TI recommends monitoring the OTW
signal using the system microcontroller and re-
sponding to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device resulting in device shutdown
(OTE).
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
two protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing, i.e., it performs
a current-limiting function rather than prematurely
shutting down during combinations of high-level mu-
sic transients and extreme speaker load impedance
drops. If the high-current situation persists, i.e., the
power stage is being overloaded, a second protection
system triggers a latching shutdown, resulting in the
power stage being set in the high-impedance (Hi-Z)
state. Current limiting and overload protection are
independent for half-bridges A and B and, respect-
ively, C and D. That is, if the bridge-tied load between
half-bridges A and B causes an overload fault, only
half-bridges A and B are shut down.
To reduce external component count, an internal
pullup resistor to 3.3 V is provided on both SD and
OTW outputs. Level compliance for 5-V logic can be
obtained by adding external pullup resistors to 5 V
(see the
Electrical Characteristics
section of this data
sheet for further specifications).
circuits,
overload,
21