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參數(shù)資料
| 型號： | TAS5086DBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, TSSOP-38 |
| 文件頁數(shù)： | 44/47頁 |
| 文件大?。?/td> | 814K |
| 代理商： | TAS5086DBTG4 |
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TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
SDA
SCL
tf
tSU-DAT
tHD-STA
tr
tBUF
tSU-STO
P
S
tSP
tSU-STA
Sr
tHIGH
tHD-DAT
tLOW
tr
tHD-STA
S
tf
T0114-01
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
Devices
All values are referred to VIHmin and VILmax (see TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for
A
STANDARD MODE
FAST MODE
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
fSCL
SCL clock frequency
0
100
0
400
kHz
Hold time (repeated) START condition.
tHD-STA
After this period, the first clock pulse is
4
0.6
s
generated.
tLOW
LOW period of the SCL clock
4.7
1.3
s
tHIGH
HIGH period of the SCL clock
4
0.6
s
tSU-STA
Setup time for repeated START
4.7
0.6
s
tSU-DAT
Data setup time
250
100
s
tHD-DAT
Data hold time (1)(2)
0
3.45
0
0.9
s
tr
Rise time of both SDA and SCL
1000
7 + 0.1 Cb
(3)
500(4)
ns
tf
Fall time of both SDA and SCL
300
7 + 0.1 Cb
(3)
300
ns
tSU-STO
Setup time for STOP condition
4
0.6
s
tBUF
Bus free time between a STOP and
4.7
1.3
s
START condition
Cb
Capacitive loads for each bus line
400
pF
Noise margin at the LOW level for each
VnL
0.1 VDD
V
connected device (including hysteresis)
Noise margin at the HIGH level for each
VnH
0.2 VDD
V
connected device (including hysteresis)
(1)
Note that SDA does not have the standard I2C specification 300-ns hold time and that SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 3.3-k
pullup resistor be used to avoid potential timing issues.
(2)
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
(3)
Cb = total capacitance of one bus line in pF.
(4)
Rise time varies with pullup resistor.
Figure 3. Start and Stop Conditions Timing Waveforms
6
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5086
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