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參數(shù)資料
| 型號(hào)： | TAS5086DBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, TSSOP-38 |
| 文件頁數(shù)： | 43/47頁 |
| 文件大?。?/td> | 814K |
| 代理商： | TAS5086DBTG4 |
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Serial Audio Port
t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN SCLK input frequency
CL = 30 pF, SCLK = 64 fS
2.048
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
32
48
192
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK
SCLK rising edges between LRCLK rising edges
64
edges
LRCLK clock edge with respect to the falling edge of
SCLK
–1/4
1/4
SCLK
period
Figure 2. Slave Mode Serial Data Interface Timing
Devices
STANDARD MODE
FAST MODE
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
VIL
LOW-level input voltage
–0.5
0.3 VDD
–0.5
0.3 VDD
V
VIH
HIGH-level input voltage
0.7 VDD
V
Vhys
Hysteresis of Schmitt-trigger inputs
N/A
0.05 VDD
V
LOW-level output voltage (open drain or
VOL1
3-mA sink current
0
0.4
V
open collector)
Bus capacitance from 10 pF
7 + 0.1 Cb
tof
Output fall time from VIHmin to VILmax
250
ns
to 400 pF
(1)
tSP
Pulse duration of spikes suppressed(2)
N/A
0
30
ns
Ii
Input current, each I/O pin
–30
30
–30(3)
30(3)
A
Ci
Capacitance, each I/O pin
10
pF
(1)
Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I
2C specification.
(2)
SCL and SDA have a 30-ns glitch filter.
(3)
The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
Copyright 2005–2008, Texas Instruments Incorporated
5
Product Folder Link(s): TAS5086
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