
SERIAL CONTROL INTERFACE REGISTER SUMMARY
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
Channel delay
Enable/disable automatic MCLK and data-rate detection
Manual or automatic MCLK and data-rate setting
Enable/disable dc blocking
Hard/soft unmute from clock error
Default values are in bold, table values "X" equals don't care and table values "–" equals an expansion of the table for
detailed description of the respective bit.
NO. OF
SUBADDRESS
REGISTER NAME
CONTENTS
INITIALIZATION VALUE
BYTES
0x00
Clock control register
1
Description shown in subsequent section
6C
0x01
Device ID register
1
Description shown in subsequent section
03
0x02
Error status register
1
Description shown in subsequent section
00
0x03
System control register 1
1
Description shown in subsequent section
A0
0x04
Serial data interface register
1
Description shown in subsequent section
05
0x05
System control register 2
1
Description shown in subsequent section
60
0x06
Soft mute register
1
Description shown in subsequent section
00
0x07
Master volume
1
Description shown in subsequent section
FF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
30 (0 dB)
0x0B
Channel 4 vol
1
Description shown in subsequent section
30 (0 dB)
0x0C
Channel 5 vol
1
Description shown in subsequent section
30 (0 dB)
0x0D
Channel 6 vol
1
Description shown in subsequent section
30 (0 dB)
0x0E
Volume control register
1
Description shown in subsequent section
B1
0x0F
RESERVED(1)
0x10
Modulation limit register
1
Description shown in subsequent section
02
0x11–0x17
RESERVED(1)
0x18
PWM start register
1
Description shown in subsequent section
3F
0x19
Surround register
1
Description shown in subsequent section
00
0x1A
Split cap charge period register
1
Description shown in subsequent section
18
0x1B
OSC_TRIM
1
Oscillator trim register
82
0x1C
BKNDERR register
1
BKNDErr Register
05
0x1D–0x1F
RESERVED(1)
0x20
Input MUX register
4
Description shown in subsequent section
0x00, 0x01, 0x23, 0x45
0x21
Downmix input MUX register
4
Description shown in subsequent section
0x00, 0x00, 0x40, 0x3F
0x22
AM tuned frequency
4
Description shown in subsequent section
0x00, 0x00, 0x00, 0x00
0x23
ch6_bq[1]
20
b0[25:24] b0[(23:16], b0[15:8], b0[7:0]
0x00, 0x80, 0x00, 0x00
b1[25:24] b1[23:16], b1[15:8], b1[7:0]
0x00, 0x00, 0x00, 0x00
b2[25:24] b2[23:16], b2[15:8], b2[7:0]
0x00, 0x00, 0x00, 0x00
a1[25:24] a1[23:16], a1[15:8], a1[7:0]
0x00, 0x00, 0x00, 0x00
a2[25:24] a2[23:16], a2[15:8], a2[7:0]
0x00, 0x00, 0x00, 0x00
0x24
ch6_bq[2]
20
b0[25:24] b0[23:16], b0[15:8], b0[7:0]
0x00, 0x80, 0x00, 0x00
b1[25:24] b1[23:16], b1[15:8], b1[7:0]
0x00, 0x00, 0x00, 0x00
b2[25:24] b2[23:16], b2[15:8], b2[7:0]
0x00, 0x00, 0x00, 0x00
a1[25:24] a1[23:16], a1[15:8], a1[7:0]
0x00, 0x00, 0x00, 0x00
a2[25:24] a2[23:16], a2[15:8], a2[7:0]
0x00, 0x00, 0x00, 0x00
(1)
Reserved registers should not be accessed.
26
Copyright 2005–2008, Texas Instruments Incorporated