參數(shù)資料
型號(hào)： TAS5076PFCR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： GREEN, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 33/64頁(yè)
文件大小： 873K
代理商： TAS5076PFCR
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
33
SLES090A—November 2003—Revised January 2004
TAS5076
4
System Procedures for Initialization, Changing Data Rates, and
Switching Between Master and Slave Modes
4.1
System Initialization
Reset is used during system initialization to hold the TAS5076 inactive while power (VDD), the master clock
(MCLK_IN), the device control, and the data signals become stable. The recommended initialization
sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control
signals (MUTE, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable.
Figure 41 shows the recommended sequence and timing for the RESET terminal relative to system VDD
voltage and MCLK.
MCLK
VDD
3 V
24 MCLK_IN Cycles
RESET
Figure 41. RESET During System Initialization
Within the first 2 ms following the low-to-high transition of the RESET terminal, the serial data interface format
must be set in the serial data interface control register using the I2C serial control interface. If the data rate
setting is other than the setting specified by the DBSPD terminal, then the data rate must be set using the
DBSPD terminal or I2C interface within 2 ms following the low-to-high transition of the RESET terminal.
The time available to set the I2C registers following the low-to-high transition of the RESET terminal can be
extended using the ERR_RCVRY terminal. While ERR_RCVRY is low, the TAS5076 outputs are held inactive.
Once the I2C control registers are set, the ERR_RCVRY terminal can be released and the TAS5076 starts
operation. Figure 42 shows how the ERR_RCVRY terminal can be used to extend the interval as long as
necessary to set the I2C registers following the low-to-high transition of the RESET terminal.
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