參數(shù)資料
型號(hào): TAS5076PFCR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: GREEN, PLASTIC, TQFP-80
文件頁數(shù): 20/64頁
文件大?。?/td> 873K
代理商: TAS5076PFCR
Architecture Overview
21
SLES090A—November 2003—Revised January 2004
TAS5076
During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error
recovery register bit is returned to the normal operation state. Table 211 shows the device output signal
states during error recovery.
Table 211. Device Outputs During Error Recovery
SIGNAL
MODE
SIGNAL STATE
Valid 1Valid 6
All
Low
PWM_P outputs
All
Low
PWM_M outputs
All
Low
MCLK_OUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.
2.4.3 Individual Channel Error Recovery
Individual channel error recovery is used to provide error management and to permit the PWM output to be
turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery
register to low.
While the error recover bits are brought low, the valid signals go to the low state. When the error recovery bits
are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.
The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is
selectable. This delay can be selected to be either 6
s or 47 s.
The TAS5076 controls the relative timing of the pseudo-differential drive control signals plus the valid signal
to minimize the production of system noise during error recovery operations. The transitions to valid low and
valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset
present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of
±1.56% of full scale. The default value is zero correction represented by 00h. These values can be changed
at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default
interchannel delay for the first channel and the interchannel delay between subsequent channels are mask
programmable. The present values are 0 for the first channel with increments of 53 for each successive
channel.
These values can be updated upon power up through the serial control interface. This delay is generated in
the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface.
The optimum value for interchannel delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following TC delay values
be set instead of the default value. These TC delay values in conjunction with the ABD delay value (see
discussion in Section 2.4.6) deliver the best performance in the TAS5076-5182 EVM board.
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