參數(shù)資料
型號: TAS5066PAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 46/66頁
文件大?。?/td> 1023K
代理商: TAS5066PAGR
Specifications
44
SLES089—January 2004
TAS5066
5.4.2 Serial Audio Port
5.4.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
Frequency, SCLK
12.288
MHz
tsu(SDIN)
SDIN setup time before SCLK rising edge
20
ns
th(SDIN)
SDIN hold time before SCLK rising edge
10
ns
f(LRCLK)
LRCLK frequency
32
48
192
kHz
MCLK_IN duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
tsu(LRCLK)
LRCLK setup time before SCLK rising edge
20
ns
MCLK high and low time
20
ns
5.4.2.2
Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended
Operating Conditions (Unless Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
t(MSD)
MCLK_IN to SCLK
0
5
ns
t(MLRD)
MCLK_IN to LRCLK
0
5
ns
5.4.2.3
DSP Serial Interface Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
12.288
MHz
td(FS)
Delay time, SCLK rising to Fs
ns
tw(FSHIGH)
Pulse duration, sync
1/(64
×Fs)
ns
tsu(SDIN)
SDIN and LRCLK setup time before SCLK falling edge
20
ns
th(SDIN)
SDIN and LRCLK hold time from SCLK falling edge
10
ns
SCLK duty cycle
50%
th(SDIN)
tsu(SDIN)
SCLK
SDIN
Figure 56. Right-Justified, I2S, Left-Justified Serial Protocol Timing
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