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參數(shù)資料
| 型號(hào)： | TAS5066PAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 2/66頁(yè) |
| 文件大?。?/td> | 1023K |
| 代理商： | TAS5066PAGR |
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Introduction
4
SLES089—January 2004
TAS5066
1.4
Ordering Information
Texas Instruments
T
AS
Audio Solutions
5066
PAG
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC 64-PIN TQFP
(PAG)
0
°C to 70°C
TAS5066PAG
1.5
Terminal Functions
TERMINAL
FUNCTION
DESCRIPTION
NAME
NO.
FUNCTION
DESCRIPTION
AVDD_OSC
64
P
Analog power supply for internal oscillator cells
AVDD_PLL
3
P
3.3-V analog power supply for PLL
AVSS_OSC
61
O
Analog ground for internal oscillator cells
AVSS_PLL
6
P
Analog ground for PLL
CLIP
18
O
Digital clipping indicator, active low
CS0
15
I
I2C device address select. This is an active high pin.
DBSPD
17
I
Sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_SEL1
29
I
De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DEM_SEL2
28
I
De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)
DVDD_PWM
45
P
3.3-V digital power supply for PWM
DVDD_RCL
48
P
3.3-V digital power supply for re-clocker
DVDD
25
P
3.3-V digital power supply for digital core and most of I/O buffers
DVSS
60
I
Voltage regulator enable, active low
DVSS_PWM
44
P
Digital ground for PWM
DVSS_RCL
47
P
Digital ground for re-clocker
DVSS1
8, 16
26, 31,
32
P
Digital ground for digital core and most of I/O buffers
ERR_RCVRY
10
I
Error recovery, active low
LRCLK
24
I/O
Serial audio data left/right clock (sampling rate clock) (input when M_S = 0; output when
M_S = 1)
M_S
30
I
Master/slave mode input signal (master = 1, slave = 0)
MCLK_IN
2
I
MCLK input, slave mode
MCLK_OUT
22
O
MCLK output buffered system clock output M_S = 1; otherwise set to 0
MUTE
11
I
Mute input signal, active low
I = input; O = output; I/O = input/output; P = power
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