參數(shù)資料
型號: TA2024
廠商: Electronic Theatre Controls, Inc.
元件分類: 運(yùn)動控制電子
英文描述: Stereo 10W (4з) Class-T⑩ Digital Audio Amplifier using Digital Power Processing⑩ Technology
中文描述: 10W的立體聲(4з)類- T的數(shù)字音頻放大器⑩使用數(shù)字電源技術(shù)處理⑩
文件頁數(shù): 4/14頁
文件大?。?/td> 467K
代理商: TA2024
T E C H N I C A L I N F O R M A T I O N
Page 4
TA2024 Preliminary, Rev. 1.0
Pin Description
Pin
2, 3
Function
DCAP2, DCAP1
Description
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
4, 9
5, 8,
17
6
7
10, 14
11, 15
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
VP1, VP2
IN1, IN2
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground
Bridged outputs
12
MUTE
16
18
BIASCAP
SLEEP
19
FAULT
20, 35
22
24, 27;
31, 28
25, 26,
29, 30
13, 21,
23, 32,
34
33
36
1
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD2
VDD1, VDD1
NC
Supply pins for high current H-bridges, nominally 12VDC.
Not connected. Not bonded internally.
VDDA
CPUMP
5VGEN
Analog 12VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
FAULT
PGND2
NC
NC
DGND
VDD2
OUTP2
OUTM2
VDD2
OUTM1
VDD1
VDD1
NC
OUTP1
VDDA
NC
PGND1
CPUMP
DCAP2
DCAP1
AGND3
SLEEP
BIASCAP
IN2
VP2
MUTE
NC
IN1
VP1
V5A
AGND2
OVERLOADB
REF
AGND1
V5D
30
29
19
20
21
22
23
24
25
26
27
28
1
2
15
16
17
18
14
13
11
12
10
9
8
7
6
5
4
3
36-pin Power SOP Package
(Top View)
+5VGEN
36
35
31
32
33
34
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