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參數(shù)資料
| 型號： | TA1317N |
| 元件分類： | 偏轉 |
| 英文描述： | VERTICAL DEFLECTION IC, PDIP24 |
| 封裝： | 0.300 INCH, 1.78 MM PITCH, PLASTIC, SDIP-24 |
| 文件頁數(shù)： | 44/56頁 |
| 文件大?。?/td> | 872K |
| 代理商： | TA1317N |
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TA1317N
2000-05-18
49/56
Test Condition
SW Mode
Note
No.
Parameter
SW5
SW6
SW7
SW8
SW10
SW11
SW17
SW24
Test Method
(unless otherwise specified, VCC = 9 V, Ta = 25 ± 3°C, data = preset values)
32
Vertical DF phase adjustment
(V DF phase)
OFF
B
ON
OFF
B
ON
A
(1) Input vertical trigger pulse to pin VIN.
Pulse level (VT)
= 3.0 V
(2) Set V-DF PHASE (sub-address: 06) to minimum (data: 08) and measure pin 18
(V-DF OUT) phase TVD (08).
(3) Set V-DF PHASE (sub-address: 06) to maximum (data: F8) and measure pin 18
(V-DF OUT) phase TVD (F8).
(4) Calculate change amount TVD using the following formula.
TVD = TVD (08) + TVD (F8)
33
LVP detection voltage
OFF
B
ON
OFF
B
ON
B
A
(1) Connect external supply voltage V7 to TP17 (LVP).
(2) Decrease external supply voltage V7 from 9 V. When D5 data in Read mode
changes from 0 to 1, measure TP17 voltage VLVP.
34
Vertical guard detection
voltage
OFF
C
ON
OFF
B
ON
A
(1) Connect external supply voltage V6 to TP6 (V NF).
(2) Switch to VD (sub-address: 00) to AC-Coupling mode (data: 81).
(3) Increase external supply voltage V6 from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP6 voltage VVGH.
(4) Decrease external supply voltage V6 from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP6 voltage VVGL.
Pin 18 (V-DF OUT) waveform
TVD (F8)
TVD (08)
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