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參數(shù)資料
| 型號(hào)： | TA1317N |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | VERTICAL DEFLECTION IC, PDIP24 |
| 封裝： | 0.300 INCH, 1.78 MM PITCH, PLASTIC, SDIP-24 |
| 文件頁(yè)數(shù)： | 3/56頁(yè) |
| 文件大?。?/td> | 872K |
| 代理商： | TA1317N |
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TA1317N
2000-05-18
11/56
Register Name/Number of Bits
Function Explanation
Output Change
Picture Change
Preset
V-EHT COMPENSATION/3
Adjusts the compensated rate for the V-DRIVE by EHT-IN
(pin 3).
000: 0%
111:
+10%
0%
(000)
ANALOG V-BLK STOP PHASE/5
Sets the analog blanking stop phase on pin 20. Inputs the
output from pin 20 to an external BLK-IN of synchronization
IC.
00000:
570 mV
10000: 0 mV
11111:
+570 mV
0 mV
(10000)
H-EHT COMPENSATION/3
Adjusts the compensated rate for the EW output by EHT-IN
(pin 3).
000: 0%
111:
+4.3%
0%
(000)
ANALOG V-BLK START PHASE/5
Sets the analog blanking start phase on pin 20. Inputs the
output from pin 20 to external BLK-IN of synchronization IC.
00000:
570 mV
10000: 0 mV
11111:
+570 mV
0 mV
(10000)
V-RAMP LIMIT LEVEL/4
Sets the V-ramp slice level.
0000: OFF
0001: upper 10.7%
1111: upper 37.3%
lower 17.3%
lower 46.0%
Sub-address 05-D0 bit be comes MSB.
OFF
(0000)
Pin 6
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Dashed line
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Dashed line
Pin 6
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Dashed line
Pin 11
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