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參數(shù)資料
| 型號： | TA1317ANG |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP24 |
| 封裝： | 0.300 INCH, 1.78 MM PITCH, PLASTIC, SDIP-24 |
| 文件頁數(shù)： | 10/59頁 |
| 文件大小： | 1033K |
| 代理商： | TA1317ANG |
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TA1317ANG
2005-08-18
18
Data Transmit Format 1
Data Transmit Format 2
Data Receive Format
At the moment of the first acknowledge, the master transmitter becomes a receiver and the slave receiver
becomes a transmitter.
The Stop condition is generated by the master.
Optional Data Transmit Format: Automatic Increment Mode
In this transmission method, sub-addresses are incremented automatically and data is set from the specified
sub-address.
I
2C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
1.5
V
High level input voltage
VIH
2.7
Vcc
V
Low level output voltage at 3 mA sink current
VOL1
0
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
10
10
A
Capacitance for each I/O pin
Ci
10
pF
SCL clock frequency
fSCL
0
100
kHz
Hold time START condition
tHD;STA
4.0
s
Low period of SCL clock
tLOW
4.7
s
High period of SCL clock
tHIGH
4.0
s
Set-up time for a repeated START condition
tSU;STA
4.7
s
Data hold time
tHD;DAT
100
ns
Data set-up time
tSU;DAT
250
ns
Set-up time for STOP condition
tSU;STO
4.0
s
Bus free time between a STOP and START condition
tBUF
4.7
s
S
Slave address
0 A
Transmit data
A
Sub address
A P
7 bit
MSB
S: Start condition
8 bit
MSB
A: Acknowledge
9 bit
MSB
P: Stop condition
S
Slave address
0 A
Transmit data
A
Sub address
A
Transmit data n
A
Sub address
A P
S
Slave address
1 A
A
Receive data
P
7 bit
MSB
8 bit
MSB
S
Slave address
A
Transmit data 2
Transmit data 1
A P
7 bit
MSB
8 bit
MSB
0
Sub address
7 bit
MSB
A 1
8 bit
MSB
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