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參數(shù)資料
| 型號： | TA1204AF |
| 廠商： | Toshiba Corporation |
| 英文描述： | ャ CORRECTION IC FOR LCD TV |
| 中文描述： | ャ校正集成電路液晶電視 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大?。?/td> | 575K |
| 代理商： | TA1204AF |
TA1204AF
2001-02-07 18/25
Note 27:
Typical common electrode signal center voltage
Test condition 4
Input : no signal
Obtain the mean value of H and L levels in the output waveform at pin 10 and set this as the center
voltage.
Note 28:
Maximum and minimum common electrode signal center voltage variable ranges
Test condition 4
Input : no signal
VR8 :
→
Max /
→
Min
Keep pin 11 shorted with V
CC
(5V). Change SW
8
from OFF to ON, turn VR8 clockwise and
anticlockwise and thus obtain the upper limit (maximum center voltage) and the lower limit
(minimum center voltage) in a potential change at pin 10.
Note 29:
Common electrode signal output through-rate
Test condition 4
Input : no signal
Measure the 10 to 90% rise and fall times in the change between the H and L levels for the output
waveform of pin 10, and convert these into through-rates.
Note 30:
Clamp signal output, threshold 1
Test condition 6
Adjust VR34 and VR40 so that the voltage at pins 34 and 40 becomes 0.9V. Gradually raise from 0V
the direct current voltage applied to CP A In (pin 3), and measure the voltage at CP A In when the
normal voltage of 9.0±0.4V is output from G output pin (pin 19). Change SW
2M
from a to b, and
make similar measurements for CP B In (pin 4).
Note 31:
Clamp signal input threshold 2
Test condition 4 (CP mode)
Input : no signal
Change to DC the CP that is applied to CP A In (pin 3), gradually raise its voltage from 2.5V, and
measure the voltage at CP A In (pin 3) when the voltage of channel A G input pin (pin 3) is clamped
at 0.9±0.1V. Change SW
2B
from a to b, and make similar measurements for CP B In (pin 4), at
channel B G input pin (pin 40).
Note 32:
Input-switching signal threshold
Test condition 2 (direct coupling mode)
Input : no signal
Adjust VR34 and VR40 so that the voltage of pin 34 is 0.9V and that of pin 40 at 1.6V. Change SW
2A
from a to b, gradually raise from 0V the DC voltage at A / B Select (pin 2), and measure the pin 2
voltage when the output signal of G output pin 19 changes from the white level to the black level.
(Voltage difference from the
γ
0 level must be within 0.4V.)
Note 33:
Reversed polarity signal threshold
Test condition 5 (CP mode, fixed polarity)
Input : no signal
Change SW
7A
from a to b, gradually raise from 0V the DC voltage applied at Pol ln pin (7), and
measure the pin 7 voltage when the output voltage of G output pin 19 exceeds 6.5V (rapidly rising
from about 4V to about 9V).
Note 34:
Reversed polarity phase-switching signal threshold
Test condition 5 (CP mode, fixed polarity)
Input : no signal
Change SW
6A
from a to b, gradually raise from 0V the DC voltage applied at pin 6, and measure the
pin 6 voltage at the time the output voltage of G output pin 19 exceeds 6.5V (rapidly rising from
about 4V to about 9V).
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