參數(shù)資料
型號(hào): T89C5115-SISIM
廠商: Atmel
文件頁(yè)數(shù): 6/113頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28PLCC
標(biāo)準(zhǔn)包裝: 37
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
2007-2011 Microchip Technology Inc.
DS70265E-page 103
dsPIC33FJ12MC201/202
8.0
OSCILLATOR
CONFIGURATION
The
dsPIC33FJ12MC201/202
oscillator
system
provides:
External and internal oscillator options as clock
sources
An on-chip Phase-Locked Loop (PLL) to scale the
internal operating frequency to the required
system clock frequency
An internal FRC oscillator that can also be used
with the PLL, thereby allowing full-speed opera-
tion without any external clock generation hard-
ware
Clock switching between various clock sources
Programmable clock postscaler for system power
savings
A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
A Clock Control register (OSCCON)
Nonvolatile Configuration bits for main oscillator
selection
A simplified diagram of the oscillator system is shown
FIGURE 8-1:
dsPIC33FJ12MC201/202 OSCILLATOR SYSTEM DIAGRAM
Note 1:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer
to
Section
7.
“Oscillator”
(DS70186) of the “dsPIC33F/PIC24H
Family Reference Manual”
, which is
(www.microchip.com).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
Note
1:
See Figure 8-2 for PLL details.
2:
If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 M
Ω must be connected.
3:
The term FP refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this document,
FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used with
a Doze ratio of 1:2 or lower.
Secondary Oscillator
LPOSCEN
SOSCO
SOSCI
Timer 1
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FSCM
FRCDIVN
SOSC
FRCDIV16
ECPLL, FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
S4
÷16
Clock Switch
S7
Clock Fail
÷ 2
TUN<5:0>
PLL(1)
FCY
FOSC
F
RCDIV
DOZE
OSC2
OSC1
Primary Oscillator
R(2)
POSCMD<1:0>
FP
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