Figure 14. Column Latches Loading Procedure(1) Note: 1. The last page add" />
參數(shù)資料
型號: T89C5115-SISIM
廠商: Atmel
文件頁數(shù): 44/113頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28PLCC
標準包裝: 37
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
36
AT89C5115
4128G–8051–02/08
Figure 14. Column Latches Loading Procedure(1)
Note:
1. The last page address used when loading the column latch is the one used to select
the page programming address.
Programming the Flash Spaces
User
The following procedure is used to program the User space and is summarized in
Load up to one page of data in the column latches from address 0000h to 3FFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in
FCON register.This step must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Extra Row
The following procedure is used to program the Extra Row space and is summarized in
Load data in the column latches from address FF80h to FFFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 52h followed by A2h in
FCON register. This step of the procedure must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Column Latches
Loading
Data Load
DPTR = Address
ACC = Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Column Latches Mapping
FCON = 08h (FPS = 1)
Data Memory Mapping
FCON = 00h (FPS = 0)
Save & Disable IT
EA = 0
Restore IT
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