參數(shù)資料
型號(hào)： T8538B
元件分類： Codec
英文描述： T8538B Quad Programmable Codec
中文描述： T8538B四可編程編解碼器
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 847K
代理商： T8538B
20
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description
(continued)
Reset Functionality
(continued)
The reset function allows the internal logic of the
device to be set to a known initial condition, either
externally by activating the reset lead, or on a per-
channel basis through the microprocessor interface by
setting and then clearing bits, if required, in address
RESCTRL (address 128). These two reset functions
have different effects, and each of the software reset
functions is a subset of the hardware reset functional-
ity. The primary difference is in the treatment of the
internal memory. The hardware reset is assumed to be
a result of a catastrophic hardware event, such as a
loss of power or an initial powerup. Accordingly, the
assumption is made that the internal memory does not
contain valid data and default values for all memory
locations are loaded. A software reset, however, can
only be initiated if the device is operational (at least the
microprocessor interface), so the contents of the mem-
ory may indeed be valid; thus, the resets may be more
specific. Additionally, software resets only affect the
selected channel.
A 0.1
μ
F capacitor between the RST lead and ground
will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. A wait period for the internal PLL to stabilize is
required after reset goes high. See the timing diagram
shown in Figure 18 for the proper hardware or power-
on reset procedure.
For a software reset, the control memory should not be
accessed for a minimum of 256
μ
s following the reset.
Memory Control Mapping
Several memory locations are used to control the
device. The software interface tables (Table 16 and
Table 17) show the memory assignments that are use-
ful in call processing and system testing. It should be
noted that other memory locations are used by the
device to hold intermediate results and other device
state information. Writing to these other locations can
cause serious disruptions in the operation of the device
and should be avoided.
Standby Mode
The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VF
X
I and PCM signals at D
R
are ignored in this mode. BCLK must be present for
proper standby mode operation.
Test Capabilities
The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed: the first for the digital
signal from the PCM bus to be looped back to the PCM
bus. This loopback facility can be used to verify correct
operation of the PCM bus interface logic, as well as
operation of the PCM bus. The second digital loopback
function allows complete testing of the digital process-
ing capability of the codec by looping the data back at
the analog/digital conversion interface. The third loop-
back function can be used to check the operation of all
the signal processing performed in the device, includ-
ing the conversions to/from analog. These digital loop-
back functions can be used with tone generation and
reception via the PCM bus.
The first analog loopback facility is at the digital side of
the delta-sigma converters and loops analog transmit
data back to the analog receive path. The second ana-
log loopback is at the PCM bus interface and loops the
transmit data from the line back to the receive path.
By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.
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