- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T8538A (Lineage Power) Quad Programmable Codec(四通道可編程編解碼器) PDF資料下載
參數(shù)資料
| 型號： | T8538A |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad Programmable Codec(四通道可編程編解碼器) |
| 中文描述： | 四可編程編解碼器（四通道可編程編解碼器） |
| 文件頁數(shù)： | 38/42頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | T8538A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁
38
Lucent Technologies Inc.
Advance Data Sheet
October 2000
T8538A Quad Programmable Codec
Software Interface
(continued)
Table 17. Control Bit Definition
(continued)
Control
Name
(Address)
PCMCTRL1
(157)
Bit
Assignment(s)
Function
7
3-state transmit PCM interface. Defaults to zero. A one forces the PCM interface
into a high-impedance state during its assigned time-slot on the PCM bus. Plac-
ing the channel in standby mode also forces a high-impedance condition on the
transmit interface.
Transmit zeros instead of data. Defaults to zero (off).
Linear mode significant bit. A one sets MSB first for both PCM transmit data out-
put and for PCM receive data input. A zero sets both PCM paths to LSB first.
Defaults to zero, LSB first.
Place idle-channel code on receive path. Defaults to zero (off).
Loopback receive to transmit at PCM conversion interface (
digital loopback 1
).
Defaults to zero (no loopback).
Loopback transmit to receive at PCM conversion interface (
analog loopback 2
).
Defaults to zero (no loopback).
Linear/companded mode. A one sets 16-bit linear mode with two adjacent time
slots used. Linear data is in two’s complement form. Linear mode is only available
when using single-clocking mode. A zero sets companded mode with only one
time slot used. Defaults to zero. Linear mode is programmed as LSB or MSB first
using bit 5 of this word.
μ
-law or A-law. A one sets A-law mode, and a zero sets
μ
-law mode. Defaults to
zero (
μ
-law).
Load as zeros.
Controls the drivers for the corresponding SLIC latches. A one enables the lead
as an output. Defaults to 0x0C (bits 2 and 3 set, the rest cleared).
Load as zeros.
SLIC data latches. If the corresponding bit in the SLICTS address is set for an
output, the device will drive the corresponding bit according to the contents of this
address. Writes are performed on the subsequent PCM frame sync. Default is
zero.
Not used, ignore on read.
Reports the actual state of the SLIC leads. Anything written to this address is
ignored. Updates every PCM frame (125
μ
s).
Test location for serial interface. This location has no internal use, but merely
latches write data for the purpose of testing the serial interface.
6
5
4
3
2
1
0
SLICTS
(158)
6—7
0—5
SLICWR
(159)
6—7
0—5
SLICRD
(160)
6—7
0—5
VERIFY
(162)
0—7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T85HF10 | POWER RECTIFIER DIODES |
| T85HF100 | POWER RECTIFIER DIODES |
| T85HF120 | POWER RECTIFIER DIODES |
| T85HF20 | POWER RECTIFIER DIODES |
| T85HF40 | POWER RECTIFIER DIODES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8538B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8538B Quad Programmable Codec |
| T85471G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85471J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8550VBAAA | 制造商:Arcolectric 功能描述:2 Pole Miniature rocker switch(Curved) 制造商:Arcolectric 功能描述:Double Pole,Miniature rocker switch(Curved),Standard Body with Terminal Barrier |
| T8553VBNAK | 制造商:Arcolectric 功能描述:Double Pole,Miniature rocker switch(Curved lit),Standard Body with Terminal Barrier 制造商:Arcolectric 功能描述:2 Pole Mini rocker switch(Curved lit) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。