參數(shù)資料
型號(hào)： T8538A
廠商： Lineage Power
元件分類： Codec
英文描述： Quad Programmable Codec(四通道可編程編解碼器)
中文描述： 四可編程編解碼器（四通道可編程編解碼器）
文件頁數(shù)： 33/42頁
文件大小： 1019K
代理商： T8538A
Lucent Technologies Inc.
33
Advance Data Sheet
October 2000
T8538A Quad Programmable Codec
Timing Characteristics
(continued)
PCM Interface Timing
(continued)
Double-Clocking Mode
As with the single-clocking mode, FS signifies the start
of frame on the PCM bus for all four channels and
occurs every 125
μ
s at an 8 kHz rate. FS must be
synchronous with BCLK and must be high for a mini-
mum of one BCLK period. And the PCM interface oper-
ates using fixed data rate timing; data timing for both
transmit and receive are controlled by BCLK. In double-
clocking mode, however, BCLK runs at twice the PCM
data rate. BCLK can be any value from 512 kHz (data
rate of 256 kbits/s, 4 time slots) to 16.384 MHz (data
rate of 8192 kbits/s, 128 time slots) as defined by Table
15.
In Figure 21, detail A, the falling edge of the first BCLK
latches FS. The falling edge of the second BCLK
latches DR (receive bit offset of 1). DX starts on the ris-
ing edge of the first BCLK. The PCM bus transfers the
most significant bit of the data first
The codec defaults to FS and DR being latched on the
first BCLK cycle. To latch DR on the second BCLK
cycle, program receive bit offset for 1 (RXBITOFF =
0x20). For every bit programmed (0 to 7), bit offset
shifts transmit or receive data by one BCLK cycle.
Therefore, in double-clock mode, the time-slot assign-
ment and bit offset registers need to be used in tandem
in order to achieve a full range of bit offset values. For
instance, in time-slot 0, bit offset will shift data up to
four bits. To shift data 5 to 8 bits, time-slot 1 needs to
be selected.
Linear coding is not allowed in double-clocking mode.
TSX0 or TSX1 (not shown in Figure 21) is active (low)
when DX data is transmitting.
Note that the device reverts back to single-clock mode
if reset (address 128, bit 0). If reset, immediately repro-
gram double-clock mode. Internal states of the codec
can be reset without going out of double-clock mode
(address 128, bit 1).
Table 15. PCM Interface Timing: Double-Clocking Mode
(See Figure 21.)
Note: DX load = 150 pF.
Symbol
fBCLK
Parameter
Signal
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
—
—
Typ
512
1024
1536
2048
3072
4096
8192
16384
—
Max
—
—
—
—
—
—
—
—
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
—
Allowable BCLK Frequencies
—
Jitter of BCLK
100 ns in
100 ms =
1 ppm
1953
8
tBCL x 0.6
15
—
—
tBCL
50
—
9
9
—
—
tBCL
tR, tF
tWL, tWH
tR, tF
tWFH
tWFL
tSF
tHF
tDDC
tDDF
tSD
tHD
Clock Period
Clock Rise/Fall
Pulse Width
Frame Rise/Fall
Frame Width High
Frame Width Low
Frame Setup
Frame Hold
Data Delay Clock
Data Delay Frame
Data Setup
Data Hold
BCLK
BCLK
BCLK
FS
FS
FS
FS
FS
DX
DX
DR
DR
61
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCL x 0.4
—
tBCL
tBCL
7
4
—
—
7
4
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