- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T8536 (Lineage Power) Quad Programmable Codec(四通道可編程編解碼器) PDF資料下載
參數(shù)資料
| 型號(hào)： | T8536 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad Programmable Codec(四通道可編程編解碼器) |
| 中文描述： | 四可編程編解碼器（四通道可編程編解碼器） |
| 文件頁數(shù)： | 42/54頁 |
| 文件大?。?/td> | 1872K |
| 代理商： | T8536 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
42
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
T8535/T8536 Quad Programmable Codec
Timing Characteristics
(continued)
PCM Interface Timing
(continued)
Double-Clocking Mode
As with the single-clocking mode, FS signifies the start
of frame on the PCM bus for all four channels and
occurs every 125
μ
s at an 8 kHz rate. FS must be
synchronous with BCLK and must be high for a mini-
mum of one BCLK period. And the PCM interface oper-
ates using fixed data rate timing; data timing for both
transmit and receive are controlled by BCLK. In dou-
ble-clocking mode, however, BCLK runs at twice the
PCM data rate. BCLK can be any value from 512 kHz
(data rate of 256 kbits/s, 4 time slots) to 16.384 MHz
(data rate of 8192 kbits/s, 128 time slots) as defined by
Table 19.
The PCM bus transfers the most significant bit of the
time slot first. In Figure 26, the MSB of receive data is
latched on the falling BCLK edge following the first fall-
ing BCLK edge that latches FS. Transmit data starts on
the first rising edge of BCLK prior to the falling BCLK
edge that latches FS.
Figure 26 portrays a bit offset of zero. Like single-clock-
ing mode, bit offset skews the PCM transmit and/or
receive data independently from the FS reference. Up
to 7 BCLK cycles of bit offset can be employed on a
per-channel basis. This flexibility can accommodate
special timing requirements. If using the same offset for
all channels, simply use the write all channels com-
mand.
TSX0 or TSX1 (not shown in Figure 26) is active (low)
when DX data is transmitting.
Table 19. PCM Interface Timing: Double-Clocking Mode
(see Figure 26)
Note: DX load = 150 pF.
Symbol
fBCLK
Parameter
Signal
—
—
—
—
—
—
—
—
BCLK
BCLK
BCLK
FS
FS
FS
FS
FS
DX
DX
DR
DR
Min
—
—
—
—
—
—
—
—
61
—
Typ
512
1024
1536
2048
3072
4096
8192
16384
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
1953
8
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Allowable BCLK Frequencies
tBCL
tR, tF
tWL, tWH
tR, tF
tWFH
tWFL
tSF
tHF
tDDC
tDDF
tSD
tHD
Clock Period
Clock Rise/Fall
Pulse Width
Frame Rise/Fall
Frame Width High
Frame Width Low
Frame Setup
Frame Hold
Data Delay Clock
Data Delay Frame
Data Setup
Data Hold
tBCL x 0.4
—
tBCL
tBCL
7
4
—
—
7
4
tBCL x 0.6
15
—
—
tBCL
50
—
9
9
—
—
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8535 | Quad Programmable Codec(四通道可編程編解碼器) |
| T8538A | Quad Programmable Codec(四通道可編程編解碼器) |
| T85HF10 | POWER RECTIFIER DIODES |
| T85HF100 | POWER RECTIFIER DIODES |
| T85HF120 | POWER RECTIFIER DIODES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8536B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8535B/T8536B Quad Programmable Codec |
| T8538B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8538B Quad Programmable Codec |
| T85471G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85471J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8550VBAAA | 制造商:Arcolectric 功能描述:2 Pole Miniature rocker switch(Curved) 制造商:Arcolectric 功能描述:Double Pole,Miniature rocker switch(Curved),Standard Body with Terminal Barrier |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。