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參數(shù)資料
| 型號： | T8531A |
| 廠商： | Lineage Power |
| 英文描述： | Tone Processing(音調(diào)處理器件) |
| 中文描述： | 音處理（音調(diào)處理器件） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 338K |
| 代理商： | T8531A |
Lucent Technologies Inc.
3
User Manual
September 2000
T8531 and T8531A Tone Processing
Description
Host Interface
Figure 1 shows the hardware interface between the microcontroller (host) and the T8531. The interface consists of
one control signal (UPCS), one clock (UPCK), and two serial data signals (UPDI and UPDO). The interface
enables the host to read and write hardware registers internal to the T8531, and RAM internal to the DSP1627.
The interface to the RAM is used for communication with the tone-processing algorithms. To perform tone process-
ing, the DSP clock frequency (on the T8531) must be set at 81.92 MHz. The T8531A defaults to 81.92 MHz.
5-8991a(F)
Figure 1. Hardware Interface Between Host and T8531
Figure 2 shows how the tone processing functional blocks fit into the signal path.
5-3797d(F)
Figure 2. T8531 Digital ac Path with Tone Processing
MICRO-
CONTROLLER
UPCK
UPCS
UPDI
UPDO
CLOCK
CHIP SELECT
DATA IN
DATA OUT
MICROCONTROLLER
INTERFACE
DSP1627
RAM
ROM
DSP CLOCK
81.92 MHz
T8531
μ
/A-LAW
TO
LINEAR
RECV
FILTER
REL
RDG
INTER-
POLATOR
DIGITAL
∑
-
BALANCE
FILTER
LINEAR
TO
μ
/A-LAW
XMT FILTER
REL
TDG
∑
DECIMATOR
÷
64
1.024 MHz
8 kHz
PCMRX
8 kHz
PCMTX
1.024 MHz
ABS
RDG
ABS
TDG
CTZ
FILTER
∑
CID
GEN
TONE
GEN
EQ FILTER
DIAL-TONE
FILTER
DTMF
DETECTOR
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