- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7507 (Lineage Power) Quad PCM Codec with Filters,Termination Impedance, and Hybrid Balance(帶濾波器、終端阻抗和混合平衡的四PCM編解碼器) PDF資料下載
參數(shù)資料
| 型號： | T7507 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad PCM Codec with Filters,Termination Impedance, and Hybrid Balance(帶濾波器、終端阻抗和混合平衡的四PCM編解碼器) |
| 中文描述： | 四PCM編解碼器與過濾器，終端阻抗，以及混合平衡（帶濾波器，終端阻抗和混合平衡的四的PCM編解碼器） |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 554K |
| 代理商： | T7507 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
Data Sheet
August 1999
Lucent Technologies Inc.
7
Termination Impedance, and Hybrid Balance
T7507 Quad PCM Codec with Filters,
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
35
34
32
33
Symbol
Type
O
Name/Function
EN0
C
EN1
C
EN2
C
EN3
C
Enable.
Per-line data enable control for L8567 SLIC and L7583 solid-state switch. Con-
nect to EN pin of L8567 SLIC and LATCH input of L7583 switch on a per-line basis.
When low, data latch on L8567 and L7583 inputs are transparent and data will flow
through the latch. When low, data is valid on L8567 supervision outputs. When high, data
input latches on L8567 and L7583 are latched and data on L8567 supervision outputs is
not valid. These pulses are generated internally by the T7507 and are generated
sequentially when CCLK is present.
Data Output for Serial Microprocessor Interface.
Data Input for Serial Microprocessor Interface.
Control Clock for Serial Microprocessor Interface.
This is the clock for the micro inter-
face, SLIC, and switch parallel interface. This clock shifts serial information into the DI pin
during valid write-read cycles (defined by detection of valid CSEL). This clock can be
asynchronous to other system clocks.
Note:
Maximum clock frequency is 2.048 MHz.
Chip Select for Serial Microprocessor Interface (Active-Low).
Chip select for serial
microprocessor interface. An internal pull-up is on CSEL.
Inhibit Frame Separation.
If this bit is set to 0, FSEP functions as defined. If this bit is
set to 1, the width of FSEP has no effect on Dx and D
R
timing relationship. In this case,
timing is as if FSEP = 1 MCLK. An internal pull-down is on IFS.
40
41
42
DO
DI
CCLK
O
I
I
43
CSEL
I
u
44
IFS
I
d
Functional Description
PCM Interface
Four channels of PCM data input and output are
passed through two ports, D
X
and D
R
, so some type of
time-slot assignment is necessary. The scheme used
here is to utilize a timing mode of 32 time slots corre-
sponding to a fixed master clock frequency of
2.048 MHz. Transmit to PCM data is output on pin D
X,
and receive from PCM data is input on pin D
R
. Time-
slot assignment is done via the serial control data inter-
face and is fully flexible. Any channel of any codec may
be assigned to any of the 32 time slots. See Table 2 for
additional details.
Delayed or nondelayed timing is selectable via the
serial control data interface. In the nondelayed mode,
time slot 0 nominally begins on the rising edge of
FSEP In the delayed mode, time slot 0 nominally starts
on the MCLK positive edge following the negative edge
that detects FSEP The start of PCM data can be
delayed in 8 MCLK increments by programming the
time-slot bits via the microprocessor interface.
There is a single frame sync separation input pin,
FSEP This input provides two functions: it provides a
clock for internal timing, and it sets the timing offset (if
any) between the transmit and receive frames for a
given channel on the PCM highway. There must always
be an 8 kHz signal on FSEP since this input provides
the 8 kHz clock required to maintain internal timing. By
adjusting the duty cycle of FSEP the offset between
the transmit and receive frames for a given channel on
the PCM highway is set. The number of negative clock
edges minus one that occurs while FSEP is high is the
delay (in clock periods) that is placed between the ris-
ing edge of a transmit frame sign bit and the falling
edge used by the receiver to sample the sign bit. If
FSEP is high for one clock period or less, the device
makes the transmit edges and receive sampling edges
one-half clock period apart.
Alternately, the inhibit frame separation (IFS) pin can
be used to force the one-half clock period state, regard-
less of the length of FSEP If the IFS pin is tied low,
FSEP functions as defined above in determining the
PCM transmit/receive offset. If IFS is tied high, the
width of FSEP has no effect on the D
X
/D
R
timing rela-
tionship; timing is as if FSEP = 1 MCLK. Regardless of
how IFS is tied, an 8 kHz signal must still be applied to
FSEP to maintain internal timing. Tying IFS high simply
negates the effect of the duty cycle of FSEP on the D
X
/
D
R
timing relationship.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7536 | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| T7531A | 16-Channel Programmable Codec Chip Set(十六通道可編程編解碼器芯片組) |
| T7570 | Programmable PCM Codec with Hybrid-Balance Filter(帶混合平衡濾波器的可編程PCM編解碼器) |
| T7633 | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| T7688 | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T75-08M2 | 制造商:The Cherry Corporation 功能描述: |
| T-751 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:Fly Back Transformer |
| T75-24C3 | 制造商:Stancor 功能描述:Power Transformer Triple Prim. Single Sec. 120V/208V/240V Prim. 24V Sec. Flange Mount |
| T7570 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T7570 Programmable PCM Codec with Hybrid-Balance Filter |
| T-758 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:Transformer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。