參數(shù)資料
型號(hào)： T7507
廠(chǎng)商： Lineage Power
元件分類(lèi)： Codec
英文描述： Quad PCM Codec with Filters,Termination Impedance, and Hybrid Balance(帶濾波器、終端阻抗和混合平衡的四PCM編解碼器)
中文描述： 四PCM編解碼器與過(guò)濾器，終端阻抗，以及混合平衡（帶濾波器，終端阻抗和混合平衡的四的PCM編解碼器）
文件頁(yè)數(shù)： 12/30頁(yè)
文件大小： 554K
代理商： T7507
12
Lucent Technologies Inc.
Data Sheet
August 1999
Termination Impedance, and Hybrid Balance
T7507 Quad PCM Codec with Filters,
Functional Description
(continued)
Input Word Definition
The control data input on DI is an 8-bit word of the format:
C1 C0 M D4 D3 D2 D1 D0
Bits C0 and C1 are the channel select bits. Bit M is a mode control bit. Bits D0, D1, D2, and D3 are data bits. Bit D4
can be either a mode control bit or a data bit. If M is set to 0, the data word is set to the PCM time-slot assignment
mode and bit D4 is a data bit. If M is set to 1, then D4 is also a mode set bit. If M, D4 = 1, 0, then the data word rep-
resents the relay/switch control delayed/nondelayed timing mode. If M, D4 = 1, 1 then the data word represents the
codec/SLIC control mode.
* Delayed/nondelayed PCM timing is a global parameter—all channels are programmed to the most recent value. To program PCM timing, use
C0 = C1 = 0. (That is channel 0.) M = 1, D4 = 0. When programming C1, C0 = 01, M = 1, D4 = 0, then D3 must be programmed to 0. When C1,
C0 = 10, 11, M = 1, D4 = 0, then D3 is ignored.
Note: Do not assign two channels to the same time slot. If two channels are assigned to the same time slot, the result is indeterminate. It is rec-
ommended that time-slot assignment should only be done when the channel is powered down. If multiple chips are tied to the same D
X
bus, this can result in bus contention. Thus, reassignment of time slots should be done before the channel is powered up. For all codecs,
upon powerup, channel 0 will be assigned to time slot 0, channel 1 will be assigned to time slot 1, channel 2 will be assigned to time slot
2, and channel 3 will be assigned to time slot 3.
Table 3. C0, C1 Channel Select
C1
0
0
1
1
C0
0
1
0
1
Channel
0
1
2
3
Table 4. M, D4, D3, D2, D1, D0 Mode Select and Data
M
0
D4
D3
D2
D1
D0
Time-Slot
Assignment
0
Time-Slot
Assignment
Delayed/Nondelayed
PCM Timing Mode or
Reserved*
T7507 Per Channel
Powerup/Powerdown
Time-Slot
Assignment
Relay State
Control Information
3
Channel Receive
Gain
Time-Slot
Assignment
Relay State
Control Information
2
B1 SLIC Control Bit
Time-Slot
Assignment
Relay State
Control Information 1
1
1
1
B0 SLIC Control Bit
Table 5. M = 0 Mode (PCM Time-Slot Assignment)
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
1
Function
Time Slot 0
Time Slot 1
.
.
.
1
1
1
1
1
Time Slot 31
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