參數(shù)資料
型號(hào)： T7290A
廠商： Lineage Power
英文描述： DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口)
中文描述： DS1/T1/CEPT/E1線路接口（DS1/T1/CEPT/E1線接口）
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 420K
代理商： T7290A
Data Sheet
April 1998
T7290A DS1/T1/CEPT/E1 Line Interface
13
Lucent Technologies Inc.
Jitter Attenuator
(continued)
Figure 9. Jitter Attenuator Phase Response
0
50
100
150
TIME (ms)
R
20
15
10
5
0
PHASE STEP RESPONSE (I
fI = 0
→
400 Hz)
5-2485(C)r.3
Alarms and Maintenance
Digital Loss of Signal (DLOS)
A digital loss of signal (DLOS = 1) is indicated if 128 or
more consecutive 0s occur in the receive data stream
during DS1/T1 operation. During CEPT operation, a
DLOS is indicated when 32 or more consecutive 0s
occur in the receive data stream. DLOS is then deacti-
vated when the ones density exceeds 12.5% and there
are no more than 15 consecutive 0s (T1, DS1, and
CEPT), signifying the return of good signal. DLOS
deactivation monitors the data in fixed 32-bit windows.
Each window must have at least four 1s with no more
than 15 consecutive 0s. Consecutive 0s are also moni-
tored across the window boundary. This condition must
persist for two consecutive 32-bit windows, at which
time DLOS is deactivated at the end of the window.
Upon DLOS detection, RCLK is phase-locked to the
external clock (EXCLK) so that other system devices
slaved to the line clock continue to operate without
instantaneous phase hits or discontinuities. Either an
analog loss of signal (ALOS) or a digital loss of signal
(DLOS) activates the IN-LOS output pin.
Output Loss of Signal (OUT-LOS)
An output loss of signal (OUT-LOS = 1) is indicated if
either the transmit clock (TCLK) or the smoothing clock
(SCLK) output of the jitter attenuator is absent. If the jit-
ter attenuator is placed in the transmit path, SCLK is
monitored. If the jitter attenuator is not used in the
transmit path, TCLK is monitored. For every ten clock
periods of the PLL oscillator clock, denoted as
UGRCLK in Figure 1, a strobe is generated. If a single
transmit clock period occurs between strobes, then
OUT-LOS = 0. If no transmit clock period occurs
between strobes, then OUT-LOS = 1, and the output
drivers (T2 and R2) are placed into a high-impedance
state and no data is transmitted. UGRCLK is always
present, even in the absence of both EXCLK and
T1/R1 input data; therefore, UGRCLK is the most suit-
able clock for monitoring OUT-LOS.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7290A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface
T-7290A-EL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface
T-7290A--EL 制造商:Alcatel-Lucent 功能描述:DATACOM, PCM TRANSCEIVER, PDSO28
T7290A-EL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface
T-7290A--EL-DT 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
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