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參數(shù)資料
| 型號： | T71L6816A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Sixteen-port 10/100 Switch |
| 中文描述： | 16端口10/100交換機(jī) |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 820K |
| 代理商： | T71L6816A |
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3.9 Back-off Algorithm
Preliminary T71L6816A
Taiwan Memory Technology, Copy-Right reserved.
P. 9
Change to products or specifications without notice.
Publication Date:Jun. 2001
Revision:0.A
For every port that operates in half-duplex mode, the T71L6816A implements the truncated
exponential back-off algorithm compliant to IEEE 802.3 standard and the collision counter
based on per port will be restarted after every 16 consecutive collision. That is, the
T71L6816A will guarantee no packet loss if the times of consecutive collision is less
than 16.
3.10 Buffer Management
The T71L6816A provides an interface to the external 64x64K(4Mb) SSRAM which operates in
66MHz pipeline mode as the packet storage buffer. For purpose of efficiency, the T71L6816A
divide the 4Mb space to 1K pages and each page contains 512 bytes, therefore, maximum
3 pages or minimum 1 page is needed for every Ethernet packets.
3.11 Head-of-Line Blocking
One common requirement for Ethernet switch is to prevent the Head-of-Blocking problem.
In other words, in case of some ports under heavy traffic or congestion, the switch must
keep all other ports function well and don’t be affected by those congested ports.
The T71L6816A provide a alternative way to achieve above requirement while customer
disable the flow control function. Say, the T71L6816A will first check the status of
the destination port of incoming packets, the packets will be dropped if the destined
port is congested and therefore the T71L6816A can reserve the finite spaces of the packet
buffer for other normal traffic ports.
3.12 Flow Control
3.12.1 Flow Control in Full Duplex Mode
The T71L6816A support the IEEE 802.3x flow control scheme in full duplex mode. The IEEE
802.3 define the format of pause frame as follow:
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