
TE
CH
tm
5. Reference Design
Preliminary T71L6816A
Taiwan Memory Technology, Copy-Right reserved.
P. 18
Change to products or specifications without notice.
Publication Date:Jun. 2001
Revision:0.A
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6. Configuration of Serial EEPROM(24LC02)
6.1 Mapping of Configuration
Bit
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
7
6
5
4
3
2
1
0
BRDCTRL HashMode AgeEn BackMode
SnoopEn
Reserved Reserved Reserved
VLAN_1[15:8]
VLAN_1[7:0]
VLAN_2[15:8]
VLAN_2[7:0]
TrunkPort[1:0]
TrunkBase[1:0]
MPID[3:0]
Port-base setting for port 0
Port-base setting for port 1
Port-base setting for port 2
Port-base setting for port 3
Port-base setting for port 4
Port-base setting for port 5
Port-base setting for port 6
Port-base setting for port 7
Port-base setting for port 8
Port-base setting for port 9
Port-base setting for port A
Port-base setting for port B
Port-base setting for port C
Port-base setting for port D
Port-base setting for port E
Port-base setting for port F
PauseFrameSourceAddress[47:40]
PauseFrameSourceAddress[39:32]
PauseFrameSourceAddress[31:24]
PauseFrameSourceAddress[23:16]
PauseFrameSourceAddress[15: 8]
PauseFrameSourceAddress[ 7: 0]
PauseFrameOnCRC[31:24]
PauseFrameOnCRC[23:16]
PauseFrameOnCRC[15: 8]
PauseFrameOnCRC[ 7: 0]
PauseFrameOffCRC[31:24]
PauseFrameOffCRC[23:16]
PauseFrameOffCRC[15: 8]
PauseFrameOffCRC[ 7: 0]
Reserved Reserved Reserved Reserved
SPID[3:0]