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參數(shù)資料
| 型號： | T431616E-7CG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 20/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616E-7CG |
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TE
CH
tm
LVTTL Interface
T431616D/E
TM Technology Inc. reserves the right
P. 20
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
7. Transition times are measured between V
IH
and V
IL
. Transition(rise and fall) of input signals are in a fixed slope (1 ns).
3.3V
1.2k
870
30pF
Output
1.4V
50
Output
30pF
50
Z0=
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
8. t
HZ
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( t
R
/ 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time t
T
( t
R
& t
F
) = 1 ns
If t
R
or t
F
is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be
added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously) when all input signals are held "NOP" state and both
CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200us minimum is required. Then, it is recommended that LDQM/UDQM is held
"HIGH" (V
DD
levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register Set command
in step 4 to stabilize the internal circuitry of the device.
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PDF描述 |
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| T431616E-7S | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616E-7SG | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T436416A | 4M X 16 SDRAM |
| T436416A-10S | 4M X 16 SDRAM |
| T436416A-10SG | Terminal Block End Barrier; For Use With:AB1 Series Terminal Blocks; Accessory Type:End Barrier; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T431616E-7S | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616E-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T4322 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T4323 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T4333 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
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