參數(shù)資料
型號(hào): T431616C
廠商: TM Technology, Inc.
英文描述: 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述: 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù): 18/30頁(yè)
文件大?。?/td> 720K
代理商: T431616C
TE
CH
tm
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
T431616C
TM Technology Inc. reserves the right
P.18
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
C L = 2
C L = 3
W E
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H IG H
t
C C D
D Q M
D Q
:D o n 't c a re
R o w A c tiv e
(A -B n a k )
R e a d (A -
B n a k )
R e a d (A -
B n a k )
W rite (A -
B n a k )
W rite (A -
B n a k )
P re c h a rg e
(A -B n a k )
* N o te1
* N o te3
* N o te2
t
R C D
t
R D L
t
C D L
R a
C a 0
C b 0
C c 0
C d 0
Q a 0
Q a 1
Q a 0
Q a 1
Q b 0
Q b 0
Q b 1
Q b 2
Q b 1
D c 0
D c 1
D c 0
D c 1
D d 0
D d 1
D d 0
D d 2
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input,
t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
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T431616D 制造商:TMT 制造商全稱(chēng):TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM