參數(shù)資料
型號(hào): T431616A-7C
廠商: TM Technology, Inc.
英文描述: 1M x 16 SDRAM
中文描述: 100萬(wàn)× 16內(nèi)存
文件頁(yè)數(shù): 8/31頁(yè)
文件大小: 1614K
代理商: T431616A-7C
TE
CH
tm
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
T431616A
Taiwan Memory Technology, Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
Speed Version
-7
14
Parameter
Symbol
-6
12
-8
16
-10
20
Unit
Note
Row active to row active delay
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
ns
1
RAS to CAS delay
16
16
20
20
ns
1
Row precharge time
18
20
20
20
ns
1
42
42
48
50
ns
1
Row active time
100K
63
ns
ns
CLK
Row cycle time
Last data in to new col. Address delay
t
CDL
(min)
Last data in to row precharge
60
68
70
1
2
1
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
2
CLK
2
Last data in to burst stop
1
CLK
2
Col. Address to col. Address delay
1
1
1
CLK
3
Number of valid output data
ea
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
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PDF描述
T431616A-7CI 1M x 16 SDRAM
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T431616A-7SI 1M x 16 SDRAM
T431616B 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T431616A-7CI 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM
T431616A-7S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM
T431616A-7SI 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM
T431616B 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616B-10C 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM