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參數(shù)資料
| 型號： | T35L6432B |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 162K |
| 代理商： | T35L6432B |
TE
CH
tm
READ/WRITE TIMING
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P. 14
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
C L K
A D S C
A D D R E S S
B W E
B W 1 -B W 4
C E
(N O T E 2 )
O E
D
t
K C
t
K H
t
K L
:D o n 't c a re
:U N D E F IN E D
A D S P
t
A D S S
t
A D S H
A 1
A D V
B a c k -to -B a c k R E A D s
B U R S T R E A D
Q
S in g le W R IT E
B a c k -to -B a c k
W R IT E s
t
A S
t
A H
A 2
A 3
A 4
A 5
A 6
t
W S
t
W H
t
C E S
t
C E H
t
D S
t
O E H Z
t
D H
t
K Q
t
O E L Z
H ig h - Z
Q (A 1 )
Q (A 2 )
Q (A 4 )
Q (A 4 + 1 )
Q (A 4 + 2 )
Q (A 4 + 3 )
D (A 6 )
D (A 5 )
D (A 3 )
(N O T E 1 )
Note:
1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2.
CE2
and CE2 have timing identical to CE . On this diagram, when CE is LOW,
CE2
is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP
,
ADSC
or
ADV
cycle is performed.
4.
GW
is HIGH.
5. Back-to-back READs may be controlled by either
ADSP
or
ADSC
.
相關PDF資料 |
PDF描述 |
|---|---|
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
| T35L6464A | 64K x 64 SRAM |
| T35L6464A-5L | 64K x 64 SRAM |
| T35L6464A-5Q | 64K x 64 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6464A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5L | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
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