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參數(shù)資料
| 型號： | T35L6432B |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 162K |
| 代理商： | T35L6432B |
TE
CH
tm
READ TIMING
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P. 12
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
C L K
A D S C
A D D R E S S
G W ,B W E
B W 1 -B W 4
C E
(N O T E 2 )
O E
Q
t
K C
t
K H
t
K L
t
A D S S
t
A D S H
t
A S
t
A H
A 1
t
W S
t
W H
t
C E S
t
C E H
:D o n 't care
:U N D E F IN E D
A D S P
t
A D S S
t
A D S H
A 2
t
A A S
t
A A H
t
K Q L Z
t
O E Z
t
O E H Z
t
O E L Z
t
K Q
t
K Q X
Q (A 1 )
Q (A 2 )
Q (A 2 + 1 )
Q (A 2 + 2 )
Q (A 2 + 3 )
Q (A 2 + 1 )
Q (A 2 + 2 )
Q (A 2 )
A D V
t
K Q H Z
S ingle R E A D
B U R S T R E A D
B u rst w raps aro un d to
its in ital state
A D V suspen ds b urst
D eselect C ycle
(N o te4 )
t
K Q
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2
is LOW
and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled tKQHZ after diselect.
相關PDF資料 |
PDF描述 |
|---|---|
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
| T35L6464A | 64K x 64 SRAM |
| T35L6464A-5L | 64K x 64 SRAM |
| T35L6464A-5Q | 64K x 64 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6464A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5L | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
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