參數(shù)資料
型號: T35L6432B-10Q
廠商: TM Technology, Inc.
英文描述: 64K x 32 SRAM
中文描述: 64K的× 32的SRAM
文件頁數(shù): 13/16頁
文件大?。?/td> 162K
代理商: T35L6432B-10Q
TE
CH
tm
WRITE TIMING
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P. 13
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
C L K
A D S C
A D D R E S S
G W
C E
(N o te 2 )
O E
D
t
K C
t
K H
t
K L
t
A D S S
t
A D S H
t
A S
t
A H
A 1
t
C E S
t
C E H
:D o n 't c a re
:U N D E F IN E D
A D S P
t
A D S S
t
A D S H
A 2
A D V
B U R S T R E A D
B U R S T W R IT E
B W E
B W 1 -B W 4
Q
S in g le W R IT E
E x te n d B U R S T W R IT E
A 3
(N o te 4 )
(N o te 1 )
(N o te 3 )
(N o te 5 )
t
A D S S
t
A D S H
A D S C e x te n d s b u rs t
B Y T E W R IT E s ig n a ls a re
ig n o re d fo r firs t c y c le w h e n
A D S P in itia lte s b u rs t
t
W S
t
W H
t
W S
t
W H
t
A A S
t
A A H
A D V s u s p n d s b u rs t
t
D S
t
D H
t
O E H S
H ig h -Z
D ( A 1 )
D ( A 2 )
D ( A 2 + 1 )
D ( A 2 + 1 )
D ( A 2 + 2 )
D ( A 2 + 3 )
D ( A 3 )
D ( A 3 + 1 )
D ( A 3 + 2 )
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to
CE
. On this diagram, when
CE
is LOW ,
CE2
is
LOW and CE2 is HIGH. When
CE
is HIGH ,
CE2
is HIGH and CE2 is LOW.
3.
OE
must be HIGH before the input data setup and hold HIGH throughout the data hold time.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
ADV
must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE ,BW1-BW4
LOW.
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