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參數(shù)資料
| 型號： | SY89464UMYTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 689K |
| 代理商： | SY89464UMYTR |
Micrel, Inc.
SY89464U
December 2007
M9999-120607-B
hbwhelp@micrel.com or (408) 955-1690
8
Functional Description
RPE MUX and Fail-Safe Input
The SY89464U is optimized for clock switchover
applications where switching from one clock to another
clock without runt pulses (short cycles) is required. It
features two unique circuits:
Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover
between two clocks and prevents any runt pulses from
occurring during the switchover transition. The design
of both clock inputs is identical (i.e., the switchover
sequence and protection is symmetrical for both input
pairs, IN0 or IN1. Thus, either input pair may be
defined as the primary input). If not required, the RPE
function can be permanently disabled to allow the
switchover between inputs to occur immediately. If the
CAP pin is tied directly to VCC, the RPE function will be
disabled and the multiplexer will function as a normal
multiplexer.
Fail-Safe Input (FSI) Circuit
The
FSI
function
provides
protection
against
a
selected input pair that drops below the minimum
amplitude requirement. If the selected input pair drops
sufficiently below the 100mV minimum single-ended
input amplitude limit (VIN), or 200mV differentially
(VDIFF_IN), then the output will latch to the last valid
clock state.
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI
functionality is described with the following four case
descriptions. All descriptions are related to the true
inputs and outputs. The primary (or selected) clock is
called CLK1; the secondary (or alternate) clock is
called CLK2. Due to the totally asynchronous relation
of the IN and SEL signals, and an additional internal
protection against metastability, the number of pulses
required for the operations described in cases 1-4 can
vary within certain limits. Refer to “Timing Diagrams”
section for detailed information.
Case #1: Two Normal Clocks and RPE-Enabled
In this case, the frequency difference between the two
running clocks, IN0 and IN1, must not be greater than
1.5:1. For example, if the IN0 clock is 500MHz, the IN1
clock must be within the range of 334MHz to 750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur in
three stages.
Stage 1: The output will continue to follow CLK1
for a limited number of pulses.
Stage 2: The output will remain LOW for a limited
number of pulses of CLK2.
Stage 3: The output follows CLK2.
Timing Diagram 1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY89465U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS 1:10 Fanout with 2:1 Runt Pulse Eliminator MUX and Internal Termination |
| SY89465U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS 1:10 Fanout with 2:1 Runt Pulse Eliminator MUX and Internal Termination |
| SY89465UMG | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS 1:10 Fanout with 2:1 Runt Pulse Eliminator MUX and Internal Termination |
| SY89465UMG TR | 功能描述:IC CLOCK MUX 2:10 2GHZ 44-MLF RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:Precision Edge® 產(chǎn)品培訓模塊:High Bandwidth Product Overview 標準包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| SY89465UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS 1:10 Fanout with 2:1 Runt Pulse Eliminator MUX and Internal Termination |
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