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參數(shù)資料
| 型號： | SY89464UMYTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 689K |
| 代理商： | SY89464UMYTR |
Micrel, Inc.
SY89464U
December 2007
M9999-120607-B
hbwhelp@micrel.com or (408) 955-1690
7
AC Electrical Characteristics
(7)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50
to V
CC-2V; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT
≥ 400mV
1.5
2.0
GHz
tpd
Differential Propagation Delay
In-to-Q
100mV < VIN
≤ 200mV(8)
550
800
1150
ps
In-to-Q
200mV < VIN
≤ 800mV(8)
500
750
1100
ps
SEL-to-Q
RPE enabled, see Timing Diagram
17
cycles
SEL-to-Q
RPE disabled (VSEL = VCC/2)
600
1200
ps
tpd
Tempco
Differential Propagation Delay
Temperature Coefficient
500
fs/
oC
tS EN
Set-up Time
EN-to-CLK
Note 9
0
ps
tH EN
Hold Time
CLK-to-EN
Note 9
650
ps
tSKEW
Output-to-Output Skew
Note 10
5
25
ps
Part-to-Part Skew
Note 11
300
ps
tJITTER
Clock
Random Jitter
Note 12
1
psRMS
Cycle-to-Cycle Jitter
Note 13
1
psRMS
Total Jitter
Note 14
10
psPP
Crosstalk-Induced Jitter
Note 15
0.7
psRMS
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing.
70
220
ps
Notes:
7. High-frequency AC-parameters are guaranteed by design and characterization.
8. Propagation delay is measured with input tr, tf
≤ 300ps (20% to 80%) and V
IL
≥ 800mV. The propagation delay is function of the rise and
fall times at IN. See “Typical Operating Characteristics” for details.
9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
10. Output-to-Output skew is measured between two different outputs under identical transitions.
11. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
12. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
13. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
14. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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