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參數(shù)資料
| 型號(hào)： | SY89295U |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 2.5V / 3.3V 1.5 GHZ PRECISION LVPECL PROGRAMMABLE DELAY |
| 中文描述： | 為2.5V / 3.3V的1.5 GHz的精密可編程延遲的LVPECL |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | SY89295U |
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11
Precision Edge
SY89295U
Micrel
M9999-031604
hbwhelp@micrel.com or (408) 955-1690
APPLICATIONS INFORMATION
For best performance, use good high-frequency layout
techniques, filter V
CC
supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the SY89295U
data inputs and outputs.
V
BB
Reference
The VBB pin is an internally generated reference and is
available for use only by the SY89295U. When unused, this
pin should be left unconnected. Two common uses for V
BB
are to handle a single-ended PECL input, and to re-bias
inputs for AC-coupling applications.
If either IN or /IN are driven by a single-ended output,
V
BB
is used to bias the unused input. Please refer to Figure
10. The PECL signal driving the SY89295U may optionally
be inverted in this case.
When the signal is AC-coupled, V
BB
is used, as shown
in Figure 13, to re-bias IN and/or /IN. This ensures that
SY89295U inputs are within acceptable common mode
range.
In all cases, V
BB
current sinking or sourcing must be
limited to 0.5mA or less.
Setting D Input Logic Thresholds
In all designs where the SY89295U GND supply is at
zero volts, the D inputs can accommodate CMOS and TTL
level signals, as well as PECL or LVPECL. Figures 11, 12
and 14 show how to connect V
CF
and V
EF
for all possible
cases.
Cascading
Two or more SY89295U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89295U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY89295U. Using this internal circuitry, the SY89295U may
be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY89295U appear in
Figures 7, 8, and 9.
IN
/IN
Q
/Q
IN
/IN
Q
/Q
D[9:0]
#1
#2
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
Figure 7. Cascading Two SY89295U
IN
/IN
Q
/Q
IN
/IN
Q
/Q
#1
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
/CASCADE
Q
/Q
D[9:0]
#3
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 8. Cascading Three SY89295U
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89295U_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY |
| SY89295U_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz Precision LVPECL |
| SY89295U-EVAL | 制造商:Micrel Inc 功能描述:2.5V/3.3V PECL DELAY LINE - EV |
| SY89295UMG | 功能描述:延遲線/計(jì)時(shí)元素 2.5V/3.3V PECL Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89295UMG TR | 功能描述:延遲線/計(jì)時(shí)元素 2.5V/3.3V PECL Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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