參數(shù)資料
型號: SY89231UMG TR
廠商: Micrel Inc
文件頁數(shù): 13/15頁
文件大?。?/td> 0K
描述: IC CLOCK DIVIDER LVDS 16MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類型: 時鐘除法器
PLL:
輸入: CML,LVDS,PECL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 3.2GHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 帶卷 (TR)
Micrel, Inc.
SY89231U
November 2007
M9999-110507-A
hbwhelp@micrel.com or (408) 955-1690
7
Functional Description
Output Duty Cycle Equation
For a non 50% input, derate the spec by:
Divide by 3:
(0.5 -
3
100
1
X
+
) x100, in %
Divide by 5:
(0.5 -
5
100
2
X
+
) x100, in %
X= input Duty Cycle, in %
Example: if a 45% input duty cycle is applied or X=45,
in divide by 3 mode, the spec would expand by 1.67%
to 44.3%-55.7%
Enable (EN)
EN is a synchronous TTL/CMOS-compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25k
pull -up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is VCC/2.
The Enable function operates as follows:
1.
The
enable/disable
function
is
synchronous so that the clock outputs will
be enabled following a rising and a falling
edge of the input clock when switching
from EN=LOW to EN=HIGH.
However, when switching from EN=HIGH
to EN=LOW, the clock outputs will be
disabled following an input clock rising
edge and an output clock falling edge.
2.
The
enable/disable
function
always
guarantees the full pulse width at the
output
before
the
clock
outputs
are
disabled, non-depending on the divider
ratio. Refer to Figure 1b for examples.
Divider Operation
The divider operation uses both the rising and falling
edge of the input clock. For divide by 3, the falling
edge of the second input clock cycle will determine
the falling edge of the output. For divide by 5, the
falling edge of the third input clock cycle.
Refer to
Figure 1c.
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