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參數(shù)資料
| 型號(hào)： | SY89231UMG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIVIDER LVDS 16MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘除法器 |
| PLL： | 無(wú) |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.2GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
SY89231U
November 2007
M9999-110507-A
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(8)
VCC = 2.5V ±5%; RL = 100
across the outputs; T
A = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Input Operating
Frequency
VOUT
≥ 200mV
3.2
4.5
GHz
tw
Minimum Pulse Width
IN, /IN
140
ps
tpd
Differential Propagation Delay
In-to-Q
410
610
810
ps
/MR(H-L)-to-Q
210
410
610
ps
tRR
Reset Recovery Time
/MR(L-H)-to-IN
400
ps
tS EN
Set-up Time
EN-to-IN
Note 9
50
ps
tH EN
Hold Time
IN-to-EN
Note 9
250
ps
tskew
Part-to-Part Skew
Note 10
300
ps
tJITTER
Clock
Random Jitter
Note 11
1
psRMS
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Total Jitter
Note 13
10
psPP
tr, tf
Output Rise/Fall Time (20% to
80%)
At full output swing.
90
200
ps
Output Duty Cycle(÷ 3)
Duty Cycle (input): 50%; f
≤3.2GHz,
Note 14
46
54
%
Output Duty Cycle(÷ 5)
Duty Cycle (input): 50%; f
≤3.2GHz,
Note 14
47
53
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
10. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
11. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
12. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
13. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
14. For Input Duty Cycle different from 50%, see “Output Duty Cycle Equation” in “Functional Description” subsection.
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