hbwhelp@micrel.com or (408) 955-1690 12 Case #4: Input" />
參數(shù)資料
型號: SY58621LMG
廠商: Micrel Inc
文件頁數(shù): 4/20頁
文件大小: 0K
描述: TXRX 3.2GBPS CML/LVPECL 24-MLF
標(biāo)準(zhǔn)包裝: 75
系列: SY58
邏輯類型: CML/LVPECL 背板收發(fā)器,帶集成環(huán)回
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應(yīng)商設(shè)備封裝: 24-MLF?(4x4)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-2538
SY58621LMG-ND
Micrel, Inc.
SY89465U
August 2010
M9999-080510-C
hbwhelp@micrel.com or (408) 955-1690
12
Case #4: Input Clock Failure:
Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE-enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend upon rise and fall time of the input signal
and on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
Timing Diagram 4
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