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參數(shù)資料
型號: SY58621LMG
廠商: Micrel Inc
文件頁數(shù): 14/20頁
文件大小: 0K
描述: TXRX 3.2GBPS CML/LVPECL 24-MLF
標準包裝: 75
系列: SY58
邏輯類型: CML/LVPECL 背板收發(fā)器,帶集成環(huán)回
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應(yīng)商設(shè)備封裝: 24-MLF?(4x4)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-2538
SY58621LMG-ND
Micrel, Inc.
SY89465U
August 2010
M9999-080510-C
hbwhelp@micrel.com or (408) 955-1690
3
Pin Configuration
44-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
2, 5, 7, 10
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each
pin of a pair internally terminates to a VT pin through 50. Please refer to the “Input
Interface Applications” section for more details.
4, 9
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC –1.2V. They are used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01F low ESR capacitor to VCC. Due to the limited drive capability, the VREF-AC pin
is only intended to drive its respective VT pin. Maximum sink/source current is
±1.5mA. Please refer to the “Input Interface Applications” section for more details.
3, 8
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a
VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for
maximum interface flexibility. Please refer to the “Input Interface Applications” section
for more details.
13, 15, 22, 23
28, 33, 34, 41,
43, 44
VCC
Positive Power Supply: Bypass with 0.1F||0.01F low-ESR capacitors as close to
the VCC pins as possible.
39, 40
37, 38
35, 36
31, 32
29, 30
26, 27
24, 25
20, 21
18, 19
16, 17
/Q0, Q0
/Q1, Q1
/Q2, Q2
/Q3, Q3
/Q4, Q4
/Q5, Q5
/Q6, Q6
/Q7, Q7
/Q8, Q8
/Q9, Q9
Differential Outputs: These differential LVDS outputs are a logic function of the IN0,
IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
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