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參數(shù)資料
| 型號： | SY58621LMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 3.2GBPS CML/LVPECL 24-MLF |
| 標準包裝： | 75 |
| 系列： | SY58 |
| 邏輯類型： | CML/LVPECL 背板收發(fā)器，帶集成環(huán)回 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，24-MLF? |
| 供應(yīng)商設(shè)備封裝： | 24-MLF?（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1089 (CN2011-ZH PDF) |
| 其它名稱： | 576-2538 SY58621LMG-ND |
Micrel, Inc.
SY89465U
August 2010
M9999-080510-C
hbwhelp@micrel.com or (408) 955-1690
9
Functional Description
RPE MUX and Fail-Safe Input
The SY89465U is optimized for clock switchover
applications where switching from one clock to
another clock without runt pulses (short cycles) is
required. It features two unique circuits:
Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover
between two clocks and prevents any runt pulses
from occurring during the switchover transition. The
design of both clock inputs is identical (i.e., the
switchover sequence and protection is symmetrical
for both input pairs, IN0 or IN1. Thus, either input
pair may be defined as the primary input). If not
required, the RPE function can be permanently
disabled to allow the switchover between inputs to
occur immediately. If the CAP pin is tied directly to
VCC, the RPE function will be disabled and the
multiplexer will function as a normal multiplexer.
Fail-Safe Input (FSI) Circuit
The FSI function provides protection against a
selected input pair that drops below the minimum
amplitude requirement. If the selected input pair
drops sufficiently below the 100mV minimum single-
ended input amplitude limit (VIN), or 200mV
differentially (VDIFF_IN), the output will latch to the last
valid clock state.
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI
functionality is described with the following four case
descriptions. All descriptions are related to the true
inputs and outputs. The primary (or selected) clock
is called CLK1; the secondary (or alternate) clock is
called CLK2. Due to the totally asynchronous
relation of the IN and SEL signals and an additional
internal protection against metastability, the number
of pulses required for the operations described in
cases 1-4 can vary within certain limits. Refer to
“Timing Diagrams” section for detailed information.
Case #1: Two Normal Clocks and RPE Enabled
In this case, the frequency difference between the
two running clocks, IN0 and IN1, must not be greater
than 1.5:1. For example, if the IN0 clock is 500MHz,
the IN1 clock must be within the range of 334MHz to
750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur
in three stages.
Stage 1: The output will continue to follow CLK1
for a limited number of pulses.
Stage 2: The output will remain LOW for a
limited number of pulses of CLK2.
Stage 3: The output follows CLK2.
Timing Diagram 1
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參數(shù)描述 |
|---|---|
| SY58621LMG TR | 功能描述:總線收發(fā)器 4.25Gbps Transceiver w/ CML/LVPECL Outputs (I Temp, Green) RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SY58621LMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback |
| SY58626L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:DC-to-6.4Gbps Backplane Transmit Buffer with |
| SY58626L_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:DC-to-6.4Gbps Backplane Transmit Buffer with |
| SY58626LMH | 功能描述:總線發(fā)射器 6.4Gbps Transmitter w/ Pre-emphasis (Green) RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:135 Mpps 接口: 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-56 封裝:Reel |
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