參數(shù)資料
型號: SX8723E083TRT
元件分類: ADC
英文描述: 5-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO12
封裝: 4 X 4 MM, ROHS COMPLIANT, MLPD-12
文件頁數(shù): 3/53頁
文件大?。?/td> 3978K
代理商: SX8723E083TRT
ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
11
SX8723
ZoomingADC for Pressure and Temperature Sensing
GPIO
The GPIO block is a multipurpose 4 bit input/output port. In addition to digital behavior, D0 and D1 pins can be
programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an
external reference voltage (For further details see Figure 14, Figure 15, Figure 16 and Figure 17). Each port
terminal can be individually selected as digital input or output.
Figure 4 - GPIO Block Diagram
The direction of each bit within the GPIO block (input only or input/output) can be individually set using the 4
th
and 5
th bits of the RegOut register. If D[x]_DIR = 1, both the input and output buffer are active on the
corresponding GPIO block pin. If D[x]_DIR = 0, the corresponding GPIO block pin is an input only and the
output buffer is in high impedance. After power on reset the GPIO block pins are in input/output mode
(D[x]_DIR are reset to 1)
The input values of GPIO block are available in RegIn register (read only). Reading is always direct – there is
no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter
has to be realized. The input buffer is also active when the GPIO block is defined as output and the effective
value on the pin can be read back.
Data stored in the 1
st and 2nd bits of RegOut register are outputted at GPIO block if D[x]_DIR = 1. The default
values after power on reset is low (0).
The digital pins are able to deliver a driving current up to 8 mA.
When the bits VREF_D0_OUT and VREF_D1_IN in the RegMode register are set to 1 the D0 and D1 pins
digital behavior are automatically bypassed in order to either input or output the voltage reference signals.
RegOut[4]
RegOut[5]
RegOut[0]
RegIn[0]
RegOut[1]
RegIn[1]
V
REF
+
-
D1/REF
IN
D0/REF
OUT
RegMode[0]
0
1
RegMode[1]
0
1
0
1
ZoomingADC
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