參數(shù)資料
型號: SX8723E083TRT
元件分類: ADC
英文描述: 5-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO12
封裝: 4 X 4 MM, ROHS COMPLIANT, MLPD-12
文件頁數(shù): 24/53頁
文件大小: 3978K
代理商: SX8723E083TRT
ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
30
SX8723
ZoomingADC for Pressure and Temperature Sensing
ZADC Registers
Bit
Name
Mode
Reset
Description
7:0
OUT[7:0]
r
00000000
LSB of the ADC result
Table 21 - RegACOutLsb (0x50)
Bit
Name
Mode
Reset
Description
7:0
OUT[15:8]
r
00000000
MSB of the ADC result
Table 22 - RegACOutMsb (0x51)
Bit
Name
Mode
Reset
Description
7
START
rw
0
Starts an ADC conversion
6:5
SET_NELC[1:0]
rw
01
Sets the number of elementary conversions
4:2
SET_OSR[2:0]
rw
010
Sets the ADC over-sampling rate
1
CONT
rw
0
Sets continuos ADC conversion mode
0
-
r
0
unused
Table 23 - RegACCfg0 (0x52)
Bit
Name
Mode
Reset
Description
7:6
IB_AMP_ADC[1:0]
rw
11
Bias current selection for the ADC
5:4
IB_AMP_PGA[1:0]
rw
11
Bias current selection for the PGA
3:0
ENABLE[3:0]
rw
0000
ADC and PGA stage enables
Table 24 - RegACCfg1 (0x53)
Bit
Name
Mode
Reset
Description
7:6
FIN[1:0]
rw
00
ADC Sampling Frequency selection
5:4
PGA2_GAIN[1:0]
rw
00
PGA2 gain selection
3:0
PGA2_OFFSET[3:0]
rw
0000
PGA2 offset selection
Table 25 - RegACCfg2 (0x54)
Bit
Name
Mode
Reset
Description
7
PGA1_GAIN
rw
0
PGA1 gain selection
6:0
PGA3_GAIN[6:0]
rw
0001100
PGA3 gain selection
Table 26 - RegACCfg3 (0x55)
Bit
Name
Mode
Reset
Description
7
-
6:0
PGA3_OFFSET[6:0]
rw
0000000
PGA3 offset selection
Table 27 - RegACCfg4 (0x56)
Bit
Name
Mode
Reset
Description
7
BUSY
r
0
ADC activity flag
6
DEF
rw
0
Selects ADC & PGA default configuration
5:1
AMUX[4:0]
rw
00000
Input channel configuration selector
0
VMUX
rw
0
Reference source selector (VBATT = 0 or VREF = 1)
Table 28 - RegACCfg5 (0x57)
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