
PIN DESCRIPTION
11/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 2.2. Definition of Signal Pins
Signal Name
Dir
Description
Qty
BASIC CLOCKS AND RESETS
SYSRSTI#
SYSRSTO#
XTALI
XTALO
HCLK
DEV_CLK
DCLK
I
System Power Good Input
System Reset Output
14.3MHz Crystal Input
14.3MHz Crystal Output - External Oscillator Input
Host Clock (Test)
24MHz Peripheral Clock (floppy drive)
27-135MHz Graphics Dot Clock
1
1
1
1
1
1
1
O
I
I/O
I/O
O
I/O
MEMORY INTERFACE
MCLKI
MCLKO
CS#[3:0]
MA[11:0]
MD[63:0]
RAS#[1:0]
CAS#[1:0]
MWE#
DQM[7:0]
I
Memory Clock Input
Memory Clock Output
DIMM Chip Select
Memory Row & Column Address
Memory Data
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
1
1
4
O
O
O
I/O
O
O
O
O
12
64
2
2
1
8
PCI INTERFACE
PCI_CLKI
PCI_CLKO
AD[31:0]
CBE#[3:0]
FRAME#
IRDY#
TRDY#
LOCK#
DEVSEL#
STOP#
PAR
SERR#
PCIREQ#[2:0]
PCI_GNT#[2:0]
PCI_INT[3:0]
VDD5
I
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Initiator Ready
Target Ready
PCI Lock
Device Select
Stop Transaction
Parity Signal Transactions
System Error
PCI Request
PCI Grant
PCI Interrupt Request
5V Power Supply for PCI ESD protection
1
1
O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
I
O
I
I
32
4
1
1
1
1
1
1
1
1
3
3
4
4
ISA CONTROL
ISA_CLK
ISA_CLK2X
OSC14M
LA[23:17]
SA[19:0]
SD[15:0]
ALE
MEMR#, MEMW#
SMEMR#, SMEMW#
O
O
O
O
I/O
I/O
O
I/O
O
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Unlatched Address
Latched Address
Data Bus
Address Latch Enable
Memory Read and Memory Write
System Memory Read and Memory Write
1
1
1
7
20
16
1
2
2