參數(shù)資料
型號(hào): STM32F103CBT6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, LQFP-48
文件頁(yè)數(shù): 62/79頁(yè)
文件大?。?/td> 1124K
代理商: STM32F103CBT6
STM32F103xx
Electrical characteristics
Figure 28.
ADC accuracy characteristics
Figure 29.
Typical connection diagram using the ADC
1.
Refer to Table 43 for the values of CAIN, RAIN, RADC and CADC.
2.
CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 30 or Figure 31,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
EO
EG
1LSBIDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1
2
3
456
7
4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395b
VREF+
4096
(or
depending on package)]
VDDA
4096
[1LSBIDEAL =
ai14150b
STM32F103xx
VDD
AINx
IL±1 A
0.6 V
VT
RAIN(1)
CAIN
VAIN
0.6 V
VT
RADC(1)
12-bit A/D
conversion
CADC(1)
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