參數(shù)資料
型號(hào): STM32F103CBT6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, LQFP-48
文件頁數(shù): 41/79頁
文件大?。?/td> 1124K
代理商: STM32F103CBT6
Electrical characteristics
STM32F103xx
Wakeup time from low power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 7.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 25.
Low-power mode wakeup timings(1)
1.
TBD stands for to be determined.
Symbol
Parameter
Conditions
Typ
Max
Unit
tWUSLEEP
(2)
2.
The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode
Wakeup on HSI RC clock
1.8
TBD
s
tWUSTOP
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 s
3.6
TBD
s
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 s,
Regulator wakeup from LP
mode time = 5 s
5.4
9
(2) Wakeup from Standby mode
HSI RC wakeup time = 2 s,
Regulator wakeup from power
down time = 38 s
50
150
s
Table 26.
PLL characteristics
Symbol
Parameter
Test conditions
Value
Unit
Min
Typ
Max(1)
1.
Data based on device characterization, not tested in production.
fPLL_IN
PLL input clock
8.0
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
72
MHz
tLOCK
PLL lock time
200
s
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參數(shù)描述
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