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參數(shù)資料
| 型號： | STM32F103CBT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, LQFP-48 |
| 文件頁數(shù)： | 53/79頁 |
| 文件大?。?/td> | 1124K |
| 代理商： | STM32F103CBT6 |
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STM32F103xx
Electrical characteristics
5.3.15
Communications interfaces
I
2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 7.
The STM32F103xx performance line I
2C interface meets the requirements of the standard
I
2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. In addition, there is a protection
diode between the I/O pin and VDD. As a consequence, when multiple master devices are
connected to the I
2C bus, it is not possible to power off the STM32F103xx while another I2C
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
The I
2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 38.
I2C characteristics
Symbol
Parameter
Standard mode I2C(1)
1.
Values based on standard I2C protocol requirement, not tested in production.
2.
fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I
2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0(3)
3.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0(4)
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb
300
th(STA)
Start condition hold time
4.0
0.6
s
tsu(STA)
Repeated Start condition
setup time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
s
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
1.3
s
Cb
Capacitive load for each bus
line
400
pF
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| STM32F103CBT6TR | 功能描述:ARM微控制器 - MCU 32BIT Cortex M3 M/D Performance LINE RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| STM32F103CBT6XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| STM32F103CBT7 | 功能描述:ARM微控制器 - MCU 32BIT Cortex M3 M/D Performance LINE RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| STM32F103CBT7TR | 功能描述:ARM微控制器 - MCU 32-Bit ARM Cortex 128kb Performance RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| STM32F103CBT7XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
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